Motorola Inc launched its two latest PowerPC embedded chips last month. The MPC821 is designed for portable electronics, such as Personal Digital Assistants. It is essentially two chips in one, a regular PowerPC core is bundled with a Communications Processor Module, essentially another RISC processor specifically designed for signal processing applications and peripheral control. Yes that’s right, despite the previous hoo-haa about how good the PowerPC architecture is at signal processing, when it comes to real optimisation, the company still augments its capabilities with extra silicon. The MPC821’s abilities look compelling and one engineer working with Motorola described it as Essentially a 603 and a 68360 rolled into one with a dynamic RAM controller, PCMCIA port, chip select logic and some other stuff thrown in for good measure. The announcement of the chips is bolstered by a statement from Newton, Massachusetts-based Dragon Systems Inc saying the chip will support real-time continuous speech recognition. A Personal Digital Assistant that can handle continuous speech recognition? Nice, assuming that you can cram enough RAM into the machine to store the vocabulary. Mee Ling, vice-president for business development at Dragon, and the executive quoted in the Motorola press release, is not actually committing himself to converting the company’s software for the new chip, although he said he is in discussion with companies interested in building assistants based on the new chip. The PowerPC core of the MPC821 is the kind of stripped-down part seen already in previous embedded parts: there is no floating point unit and it can only issue a single instruction at a time.
Conditional pre-fetch
However it has a full complement of internal instruction queues, so that it can do branch folding, branch prediction with conditional pre-fetch, but without conditional execution. The PowerPC core is integrated with separate 4Kb data and instruction caches – both two-way set-associative. The company said that it will deliver 33 Dhrystone MIPS at 25MHz and 52 MIPS at 40MHz. The Communications Processor Module includes a simple RISC processor with multiply-accumulate hardware for the signal processor func-tions and a whole heap of input-output functions. Perhaps most important, are the two high-speed serial communications channels that can handle any of several low-layer protocols, such as Loc-alTalk or Ethernet, each channel comes with its own DMA controller. In addition, the Communications Processor Module provides two serial management controllers, a serial peripheral interface and an interprocessor-integrated communications controller. Running at 25MHz and operating at 3.3V, the processor draws 526mW. It is also possible at this clock speed to run the core of the chip at 2.2V, which pulls the requirement down to 300mW. No figures are available for power consumption at 40MHz. As with all other PowerPC embedded processors, the MPC821 comes with the ability to power-down its various functional units. At its deepest sleep level the processor only draws 40 microWatts. Elsewhere on the silicon, the processor has a memory interface which, the company said offers a glueless link to almost any memory device or memory system. The on-board liquid crystal display controller can drive a variety of grey scale and colour panels, while the PC Card controller, compliant with release 2.1 of the PCMCIA’s standard can support two independent slots. The chip is currently sampling in limited quantities with general sampling following this month and full production set for January 1996. No formal pricing has been announced, but the firm is muttering about it costing about $70 in quantities of 10,000.
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