MoSys has unveiled a roadmap for its new Bandwidth Engine integrated circuit (IC), which will combine 1T-SRAM high-density embedded memory with its 10 gigabits per second (Gbps) SerDes interface (I/O) technology and an arithmetic logic unit (ALU).
The company claims that the combination of the high-speed random access of a 1T-SRAM memory core with a serial I/O operating at 10Gbps will enable a Bandwidth Engine device to provide up to two billion accesses per second, over twice the performance of designs utilising memory technologies. Its on-chip ALU will allow macro functions to be performed within the Bandwidth Engine, reducing iterations between the other packet processing ICs and a Bandwidth Engine.
The company expects the Bandwidth Engine to enable up to four times the throughput, two to four times the density, up to 40% lower power and system cost savings of up to 50% compared with alternative offerings.
In addition, MoSys is also introducing the GigaChip Interface, an open, CEI-11 compatible chip-to-chip interface to enable serial chip-to-chip communications in networking systems. The Bandwidth engine ICs will feature the GigaChip Interface, which will be designed to achieve 90% payload bandwidth efficiency, the company said.
Content from our partners
Len Perham, president and CEO of MoSys, said: “When I returned to MoSys in late 2007, it became clear to me that our 1T-SRAM, with its advantages of up to three times the density of traditional SRAM technology, fast random access and high reliability, is a perfect solution to address the need for a dramatic increase in bandwidth in next generation switching and routing applications. We plan to continue to deliver differentiated IP to the market in the form of IP blocks that customers can integrate into their SoCs.”
The company expects to offer samples of the first Bandwidth Engine ICs in late 2010, with production quantities available in the second quarter of 2011.
