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July 8, 1997updated 05 Sep 2016 1:00pm


By CBR Staff Writer

Following Computergram’s publication of the patent Intel Corp was awarded on June 10 for a 64-bit RISC-like architecture that can accept multiple operating systems and programs with mixed instruction sets – aka Merced (CI No 3,194) – we’re grateful for chip-watchers at Electronic Engineering Times who have been poring over likely implementation scenarios. However the net result seems to be just the kind of result Intel will have wanted – more questions than answers. Given the current flurry of lawsuits being traded between semiconductor companies, the paper reckons Intel could draw fire from other companies with patents describing ways for a processor to execute RISC and CISC instructions – such as now defunct Exponential Technology. It even suggests Intel could face new legal challenges from DEC, which developed its own dual-mode processor in the 1980s. Meantime, Intel and its IA-64 instruction set partner Hewlett- Packard Co have long said its implementation, Merced, designed to be compatible with both X86 and PA-RISC instructions, will make limited used of very long-instruction-word-type (VLIW) concepts, so it should come as no surprise to readers that the paper expects Merced to be a more like a traditional RISC device than a native VLIW architecture (CI No 2,616). VLIW architectures require new compilers to get from source to object code; VLIW basically ties object code to one machine. Furthermore, given the high-level security Intel has thrown around Merced to keep details from the compatible builders (CI No 3,181), it should come as no surprise that just how many of the patented techniques Merced will use is still unclear. The patent describes how an application written in both iAPX-86 code and IA-64 code can execute on a single processor through the use of a mode bit to interpret incoming instructions. EET says the implication is that only those portions of the application software that can benefit from IA-64 need to be converted, a trick that should keep application code sizes from ballooning. It suggests Intel will opt to gradually convert to IA-64 code in much the same way that Apple migrated from the Motorola 680×0 to the PowerPC RISC. Intel describes at least five different methods of arranging the instruction cache, decoders and translator blocks before reaching the execution unit. While there’s a separate register file for RISC and CISC instruction units the paper believes there are strong indications that Merced will have a single integrated processor core. The paper says Intel’s scheme also leaves it the option of making a low-end processor providing software emulation, similar to how DEC uses a software layer to translate iAPX-86 instructions into Alpha native instructions. However Intel’s patent is more narrowly focused and takes pains to distinguish itself from other dual-mode processors such as DEC’s VAX, a processor made in the 1980s that accepted VAX code and its predecessor PDP-11 code.

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