Microprocessor companies and the multimedia industry are locked in a fierce mutual embrace. Chip makers just can’t believe their luck: the applications are just so power-hungry, the demand for extra processing power is just so great – today’s killer apps end up dead on any processor slower than a high-end 80486. And as fast as the new processors emerge, the applications designers leap on them. But will the iAPX-86-compatible manufacturers be able to keep on piling on the speed? Or will they run out of steam? Intel, in particular, has seen the way that it sells high-end chips change completely over the last few years. The old-style Intel strategy was quite straightforward: introduce a new high-end processor; aim it first at the power-hungry, deep-pocketed business market; let it trickle down into home use. Now however, the rules have changed. With the introduction of the Pentium, Intel changed tack and push its new processor into the home as well as business. After all it argued, the domestic personal computer – used for accessing CD-ROMs; tied into the Internet; used for playing high-end games – could well supplant the office desktop as the leader in the power stakes. It is set to follow the same path with its P6 or Pentium Pro.
What does Intel say the new chip will be ideal for? For 3D image processing and rendering; real-time speech recognition; smooth-motion software-only video conferencing; advanced multimedia digital sound capability, that’s what. But it wasn’t just the burgeoning multimedia market opportunity that made Intel change tack: a new level of competition was forcing it to get the new, high-margin chips into the home quickly too. There were, and are, two camps snapping at the company’s heals; the iAPX-86-cloners – Advanced Micro Devices Inc, now eating NexGen Inc, and Cyrix Corp, and the RISC makers. In the push for increased power Intel and its cloners are engaged in a spectacular contortion act: attempting to break free of the the chains that the old iAPX-86 architecture imposes, while retaining binary compatibility with existing applications. In doing so, they are producing wonderfully innovative processor designs: redefining how the processors work from the inside, while maintaining compatibility with existing applications on the outside. It’s a tough job: the iAPX-86 instruction set and architecture date back from the mid-1970s and not surprisingly, 20 years of microprocessor evolution has shown a few shortcomings. The trend today, as exemplified by the RISC chips, is to have sets of simple, fixed-length instructions. Making all instructions the same length – say one byte long – makes them simple to decode, and much easier to do microprocessors which can execute multiple instructions in parallel. The iAPX-86 set by comparison, is complex, with a plethora of variable-length instruction types. The Pentium was Intel’s first superscalar iAPX-86 chip, but its set of variable-length instructions makes it difficult to execute multiple iAPX-86 instructions in parallel. Additional problems are posed by the relative paucity of registers supported in the Intel architecture; RISC-type processors tend to have a large number of internal registers; by contrast, the iAPX-86 implements a load and store approach with fewer registers, and so more accesses to and from memory. This smaller number of registers also produces difficulties when trying to build superscalar processors: instructions executing in parallel are likely to try to compete for access to the register set. Faced with these problems Intel, Advanced Micro and Nexgen have all taken a similar approach – and built proprietary RISC processors with an iAPX-86-to-RISC translation engine on the front. At their heart, the Pentium Pro, the K5 and the Nx586 owe little or nothing to traditional iAPX-86 architecture.
By Chris Rose
Instead they have their own instruction set, their own registers, all hidden from the end user by a wrapper of iAPX-86 respectibility. The K5, for example bears more than a little resemblance to the existing Am29000 RISC; the vast majority of the designers on Intel’s Pro were recruited from its 80860 RISC operation. Nexgen’s Nx586 technology was originally designed to be able to emulate any other chip – the iAPX-86 front-end was supposed to be just the first of a series. Once the iAPX-86 instructions are converted into a series of internal RISC instructions, the chip can go to work executing them in parallel and using all the other standard RISCesque tricks of the trade. They are effectively running the iAPX-86 code in an emulation mode. None of the manufacturers has attempted to give software authors access to these internal RISC instructions – with such access, they could accelerate specific pieces of system software, screen drivers, for example. But the vendors say the internal instructions are not really suitable for direct programming, and if there is one thing the world doesn’t need, it is more instruction sets to cope with. Cyrix is the one dissentor from the hegemony. Engineers there argue that by converting the iAPX-86 to RISC instructions you don’t actually solve any problems, you simply sweep them under the carpet. Cyrix argues that the others simply have a lot of RISC engineers hanging around that dislike the messy iAPX-86 arcana and can’t wait to reshape it into a more familiar problem. Consequently Cyrix’s M1 uses kosher iAPX-86 instructions from start to finish. The speed of innovation in the iAPX-86 market has so far managed to see off the predations of the RISC manufacturers: it is often said that the biggest achievement of the PowerPC group has been the improved price-performance of the iAPX-86 manufacturers. PowerPC is far from the most powerful RISC but it scores well on price-performance, certainly beating the Pentium. But this advantage simply isn’t big enough to have made any noticeable impact on the general personal computer market. Though the processor is the most expensive component in the box, it is still only a small part of the whole package. An entire industry has grown up to service the iAPX-86-based personal computer market, and the economies of scale that this produces manages to reduce the price-performance advantage of the chip itself. On top of that, the Windows 3.1 and Windows95 operating systems are resolutely iAPX-86-only, so PowerPC has an incredibly high software hurdle to overcome. Even Windows NT still has over 90% of its sales on iAPX-86. PowerPC’s best chance of succeeding on the desktop, the best chance of making its price-performance advantage pay off, is by catching the multimedia market. Despite Intel’s protestations, users say that the lower-end 90MHz and 100MHz Pentiums really don’t cut it when it comes to the most power-hungry applications such as software-only MPEG movie play-back. To capitalise, IBM plans to ship its Sensory Suite with all PowerPC desktops. Sensory Suite, being written for AIX, Windows NT and OS/2 for PowerPC incorporates software voice control and dictation, software MPEG and a host of experimental intelligent agents based on voice control. Really good speech-to-text for free is the kind of thing that might just make the punters take a second look at PowerPC. Of course, Intel isn’t standing still and the P6 will appear in the first machines any day.
The core of the Pro contains 5.5m transistors where today’s Pentium has 3.3m. In addition the Pentium Pro has a 256Kb L2 cache on board, containing an extra 15.5m transistors. As a result, the chip package is about 40% larger than its predecessor, and it is estimated to disipate a maximum of 20 Watts at 133MHz. Both the size and the power rating will come down, however as Intel moves the manufacturing process onto a finer grade of silicon. Performance of the Pentium Pro is another unknown: the company has only announced the results of a single benchmark designed to test its integer maths performance, giving the chip a SPECint rating of 200 when running at 133MHz. Coincidentally, this is identical to the performance of the PowerPC 604 running at the same speed, implemented in 3.6m transistors. The conventional Pentium, running at the same speed has a SPECint rated at 155.5. There’s no news yet on how the new chip’s floating-point figures look, interesting since a number of the signal processing operations used in voice recognition and compression-decompression can be quite dependent on floating point performance. Last year Intel signed an agreement with Hewlett-Packard that will see the iAPX-86 and PA-RISC architecture merge by the millennium. All we know for sure is that it will run existing iAPX-86 binaries and it is sure to give the competition a run for its money.