Hewlett-Packard Co says there’s between three and five years more life left in its Precision Architecture RISC microprocessor family. The 1998 PA-8500, a 300MHz-plus device done in 0.25 micron technology with 120m transistors improves on other PA-8000 members by incorporating a whopping 1.5Mb on-board cache. A further PA-8000 part (or parts) (CI No 3,120) will improve on the existing design’s superscalar properties and would likely be fabricated in an 0.18 micron process. So why is HP, which is supposedly ‘out of the chip business,’ giving as much as five years more life to PA? No, Merced isn’t in trouble, HP says, it’s all about offering customers flexibility. So how will HP encourage customers to move across to Merced, Intel Corp’s implementation of the 64-bit IA-64 instruction set architecture which was co-developed with HP? Pervasive Solutions Foundation transition technologies, programs and finally Merced products themselves. The technologies include include single-architecture hardware, 64-bit NT and Unix operating systems and compilers and middleware that go with them. Nevertheless HP’s weighed down with a sheaf of gagging orders which prevent it from talking about the technologies in any detail. And with customers’ procurement planning schedules two, three or more years out, it’s like trying present future product plans to them gagged and blindfolded, while Scott McNealy’s UltraSparc troops are able to go in all guns blazing with tales of how UltraSparc will be ripping up the competition in the years to come. Moreover no matter how good Merced turns out to be, PA-RISC customers will still need recompile for best results. Leaving aside the few undisclosed tricks that Intel still has up its sleeve as far as the architecture is concerned – the ones it wants kept from cloners for as long as possible – Intel will have to sell the recompile for best performance to its customers as well.
Near-impossible
As far as the technology itself is concerned, PA – and IA-32 – binaries will run natively on IA-64, but run better with a recompile, though best estimates suggest anything but sample quantities of products are still two years out. HP says the technology that enables PA instructions to run on Merced combine Very Long Instruction Word and superscalar RISC techniques. Intel will be giving the technology a name, and until such time – which by all accounts should be later this year – HP won’t hang it on any particular peg. Although IA-64 processors – of which Merced will be the first iteration – will include a certain amount of hardwired PA-RISC-emulation technology, HP will be providing the additional operating system, firmware, APIs, emulation software and other techniques that will make execution of PA binaries on the processor viable. In fact it claims there’s so much it will be adding that’ll make it near-impossible, and certainly impractical in terms of what it’ll cost, for a competitor to try and build a compatible offering. (Now doesn’t that sound like a challenge?) Although Merced can be configured to run big- or little-endian code, HP will only be developing and supporting a big-endian version of HP-UX for Merced, compatible with HP-UX on its big-endian PA architecture. NT and, in all likelihood Santa Cruz Operation Inc’s 64-bit implementation of Gemini, will run on Merced systems configured to deal with the least important bits first (little-endian). We understand that Intel has a few technical tricks in store for Merced that it’s desperate to keep out of the hands of the vampire clones, hence the heavy duty security surrounding the thing. But one thing it has supposedly fixed is its historical weakness in memory management. Indeed Intel Corp a select meeting of software companies in Silicon Valley a week or so back to rah rah Merced and some of its features and allow operating system companies such as Microsoft and Santa Cruz Operation Inc to describe how they’ll be supporting the 64-bit IA-64 instruction set architecture. As usual with these matters, companies were NDA’d up to the eyeballs.
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