HP launched the initial Superdome servers back in September 2000 using a chipset with the code name Yosemite. The dome in Superdome comes from the fact that the most famous landmark in Yosemite National Park is called Half Dome, which is a place that the director of HP Labs, Dick Lampman, likes to climb. However, Half Dome is not a particularly good name for a server with which you are trying to take the world, so the product code name was changed to Superdome and HP stopped talking about the Yosemite chipset.
The Superdome name stuck, of course, and many people still call the Integrity machines–which specifically means boxes that use Itanium processors–as Superdomes. The Yosemite chipset only officially supported the PA-RISC processors–the PA-8600s, to be specific, which were the last RISC processors actually manufactured by HP–and were sold under the HP 9000 server brand.
While HP has never said this, I believe the Yosemite chipset was supposed to support the PA-RISC and the Itanium architectures side-by-side, and it was only the delay of the first generation Merced Itaniums and their poor performance that forced HP to tweak the initial Superdome hardware to support PA-8600s. The Yosemite chipset was an SMP architecture with NUMA-like properties that had a four-way cell board as the base server component; initially, HP could only scale the first Superdomes to 16-way and 32-way processing, but HP eventually pushed it to the limit of the Yosemite chipset, which was 64-way processing.
With the Pluto zx1 and Pinnacles sx1000 chipsets, HP delivered what it originally intended to deliver: a family of chipsets that could support both PA-RISC and Itanium architectures. Like the Yosemite chipset, the Pinnacles chipset could span from 16 to 64 processors in a single system image. Pinnacles really represented a rev on the chipset in terms of features, and its main benefit is that HP could build servers that used single-core PA-8700 and McKinley Itanium 2 processors and even dual-core PA-8800s using the same chipset and basic server chassis. (HP never launched a product that mixed and matched PA-RISC and Itanium processors in a single frame, but it is likely HP could have delivered such a hybrid product–and still can.)
The Pinnacles chipset did have other improvements aside from Itanium support. Its cache pipes were twice as wide (128 bytes), which doubled the bandwidth on the cache bus to 16GB/sec per cell board. Theoretical maximum main memory capacity on the Pinnacles machines was set at 128GB per cell board, the same as the Yosemite chipset, but maximum real main memory per server was extended from 512GB to 2TB with the Pinnacles chipset. However, HP never pushed that main memory above 1TB for some reason in the delivered product. Pinnacles also supported PCI and PCI-X peripherals, and added ECC error correction on the processor bus.
The Yosemite chipset had ECC on memory and I/O buses on the crossbar switch at the heart of the machine. Like the Yosemite chipset, the Pinnacles chipset supported hard partitions at the cell board level, and hot swap processor, memory, and I/O adapter cards. Both chipsets had chipkill RAID protection on memory DIMMs as well. The Pluto chipset for entry and midrange servers was one of the first chipsets actually ready for production use when the 1GHz McKinley Itanium chips were announced in the spring of 2002.
The company used the Pluto chipsets in uniprocessor and two-way workstations and servers, although it could, in theory, scale to four-way or larger configurations. To extend both the scalability of the Pluto and Pinnacles chipsets, HP rolled out dual-core PA-8800s last spring for customers needing to add processing power to their HP 9000 machines, and also created the Hondo mx2 dual Madison modules, which put two Madison Itanium 2 processors in a single package and allowed them to plug into a single Itanium 2 socket.
Content from our partners
With the Titan and Arches chipsets, says Brian Cox, product line manager for HP’s Business Critical Systems unit, the low-end and high-end HP server chipsets are going to get another rev. This time, it will be to support the PA-8900 RISC processors from HP–very likely the last PA-RISC chip that HP will deliver and almost certainly a dual-core chip very much like the PA-8800 only implemented in a smaller chip process that allows clock speeds to go up some–as well as the future dual-core Montecito Itanium processors from Intel Corp.
Cox wouldn’t say much more about these future chipsets, except that they would arrive concurrently with volume shipments of the Montecito chips from Intel. That is somewhere around late 2005 to early 2006 according to Intel, and that probably means early 2006. Cox also said the Arches chipset would support the kicker to Montecito, the Montvale Itanium processor, due in late 2006 to early 2007. I think it very likely that the Arches and Titan chipsets will support faster and wider buses and PCI Express I/O, just because the Montecito and Montvale processors will require it to get balanced performance.
Cox says HP is pretty proud of the fact that it will be able to deliver something on the order of 7 to 8 years of stability in the Superdome/Integrity family of servers, absorbing a lot of new technology without requiring customers to do forklift upgrades. CFOs like this kind of thing, and even though this is boring, boring is in, he says.
Because I/O form factors, I/O technology, processor thermals, and memory technology are changing all the time, it seems unlikely that the future Tukwila chips, due in 2007 or so and expected to have at least four cores, will be able to plug into the same physical systems and use the same chipsets. But, HP could tweak Titan and Arches and keep essentially the same chipset even if it does have to change the server chassis. Whatever HP’s plans are, Cox is not saying.
The big question left unanswered by HP concerning the Arches chipset is whether HP will keep 64 sockets in the system and use a similar cell board architecture (using either four-way or eight-way cell boards) as in the Yosemite and Pinnacles machines, or if it will do something radically different. It makes sense that HP would keep the Arches scalability to 64 sockets, since the prior Pinnacles chipset architecture already does this.
But it may turn out that 128-way processing using dual-core Montecitos just makes a lot of heat and does not do a lot of extra work. I would not be entirely surprised if HP scales back to a 32-socket machine and focuses on making that one perform better. The fact remains, whether you are talking about 64 Itanium cores or 128 Itanium cores, that is a lot more computing power than the vast majority of customers need. The issues these days are price/performance, broad operating system support, lower cost of acquisition, support, and upgrade. Winning the TPC-C benchmark test just for raw scalability can only get you so far.
It would be also interesting to see if HP would support the Opteron processors from AMD with the Arches and Titan chipsets. That would leave HP-UX in a bad position, because it has only been ported to Itanium from PA-RISC. And the memory architectures of Itanium, PA-RISC, and Opteron are so different it may be impossible. The only reason there is any affinity between Itanium and PA-RISC is because HP co-developed the chip with Intel. That said, if Arches and Titan could support Itanium, PA-RISC, and Opteron chips, HP could merge the ProLiant and Integrity lines and radically simplify its product line and marketing message.
