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February 25, 1987

DESCRIPTIONS OF NEW PRODUCTS AT INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE

By CBR Staff Writer

Some deucedly hot properties are being described at this week’s International Solid State Circuits Conference in New York, and ones rounded up by Electronic News include DEC with a 32-bit microprocessor with 1Kb of on-chip data and instruction cache and a 28-entry translation buffer; AT&T with a 32-bit RISC having 13Kb of on-chip cache; Hitachi with a mainframe chip set in 1.3 micron CMOS with a 60nS cycle; Fujitsu with a 64K ECL static RAM having a blinding 5nS access time, and Hitachi with an ECL-compatible 1.3 micron CMOS 64K static with a 7nS access time, both arranged as 8K by 8 bits; Fujitsu with a complete CMOS cache including 49K of static RAM and cache logic, with a 19nS access time; IBM with a 256K static in nanoscopic 0.7 micron CMOS with its own on-chip power supply; and Sony and Hitachi both with 1M-bit statics arranged 128 by 8, Sony’s having a 32nS and Hitachi 42nS access time.

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