Fujitsu Ltd yesterday unveiled its second generation implementation of the Sun Microsystems Sparc processor, claiming that its new part is the first RISC to break the one cycle per instruction barrier. The company claims that the first version of the new H family Sparc will offer more than twice the performance of its 25MHz S-25 version, rated at 15 MIPS. The one cycle barrier is a landmark in RISC technology because the typical best performance is 1.25 to 2.6 cycles per instruction; Fujitsu says it has a unique micro-architecture that optimises branches and load-stores, capitalising on aspects unique to the Sparc instruction set, and using existing optimising compilers. Sampling is set for second half of 1989. The company also announced the first available VLSI implementation of a 25MHz Memory Management Unit and a Floating Point Controller for a Sparc RISC, for use with its existing S-25 MB86901 part. The MB86920 memory manager for 64Gb physical, 4Gb virtual address space and the 3.3 MFLOPS single precision MB86911 floating point chip sample next month with volume in February. Volume: $239 and $238 respectively.
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