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October 15, 1998


By CBR Staff Writer

Hewlett-Packard Co has told ComputerWire that it has decided to put two new iterations of PA-RISC on the roadmap: PA-8800 and PA- 8900 (CI No 3,516) – where there had previously been blank placeholders for possibles – because its customers say that they have more important problems to consider than system transition, such as Y2K and Euro currency conversion. Moreover, HP CEO Lew Platt told the Gartner Group gathering in Orlando, Florida that Y2K issues will slow the growth of its computer business overall (CI No 3,516). HP said it always planned to do at least two more PA parts beyond the point at which Intel could offer a competitive chip. It is now talking up the PA-8900 as a 1.2GHz part that would, according to its roadmap, debut around 2004. PA-8800 is due before the end of 2003 by the same roadmap. It declined to say whether the PA-8700, which will start at 560MHz, will be the first PA part done in 0.18 micron process technology. It’s due in 2001. HP says the first run of its 0.25 micron manufacturing process delivered such good yields that it abandoned a planned PA-8550 crank of PA-8500 and is instead offering it in 240MHz and 360MHz packages. In its place it has added a PA-8600 due in 2000 clocking from 360MHz to 440MHz. Meantime, also at the Forum, HP demonstrated a new SMP system bus architecture that will support PA-RISC and IA-64 processors at Microprocessor Forum this week, but declined to say what bandwidth or performance it offers. The bus will be introduced into new PA-8500 and IA-32 systems and next year and will support board upgrades to the 64-bit Merced. The HyperPlane cross-bar distributed shared memory interconnect from its Convex Computer unit will be key to the architecture’s scalability, it says.

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