Xilinx Inc’s modular 9,000-gate XC 3090 programmable logic device, launched last week (CI No 799) is intended to be the top end member of a planned family of high-density arrays that can be easily and quickly extended. The XC 3090 programmable logic device, or PLD, is based on gate array architecture instead of the AND/OR architecture of most PLDs. Using a 1.2um double-layer metal CMOS process, Xilinx has produced circuit performances claimed to be of equal to that of gate arrays. Instead of the design being masked on to the array at the final production stage, it can be programmed and reprogrammed into the finished array and Xilinx reckons the XC 3090 can cut the time to bring a new product to market by as much as nine months. The 9,000 gate PLD, made in the San Jose-based company’s logic-cell array, which is based on static RAM technology, is capable of high gate use even at the 9,000 gate level. It features 640 user-definable logic functions and 928 flip-flops; that’s the equivalent of 9,000 two-input NAND gates. 144 programmable input/output pins are also fitted. The XC 3090 was brought in at the top end of the range, following the low end 2,400 gate XC 3020 announced back in September. With 64 logic blocks and 128 user-definable logic functions as well as 256 flip-flops, the XC 3020 will be available in volume in the second quarter of 1988 as will the XC 3090. Other devices in the family will be the 3,000-gate XC 3030, the 4,200-gate XC 3042 and the XC 3064, a 6,400-gate device. Shematic entry for the 3000 family is on the Dash and Schema II systems from the FutureNet Division of Data I/O Corp, Chatsworth, California. The PLDs will cost between $200 and $250 each in batches of 1,000 units. Xilinx expect the arrays to be supported on most major computer-aided-design workstations by the end of the year.
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