Vitesse Semiconductor Corp, Camarillo, California scored something of a coup in its campaign to prove wrong the doubters that said that Gallium Arsenide technology was too difficult to process by having Fujitsu Ltd rush to sign a second source agreement on its Fury GaAs arrays, and it is now going after ECL and BiCMOS technologies with the third generation of its H-GaAs process, in which it has shrunk the previous generation down to 0.6 micro design rules to create a process capable of reaching integration levels of over 1m GaAs transistors on a single chip. H-GaAs III, it claims, will enable microprocessors to be implemented at integration levels far in excess of next generation ECL and comparable with current CMOS and BiCMOS technologies. The basic transistor structure has been improved to achieve loaded gate delays of under 100pS while dissipating less than 200 microWatts at 1GHz clock rates. At comparable densities, BiCMOS achieves gate delays of only 250pS to 400pS and cannot support clocks above the 100MHz to 150MHz range, Vitesse reckons. H-GaAs III uses the same refractory metal self-aligned gate transistors and four layers of standard Aluminium interconnect as the previous generations and the firm says it is far less complex to fabricate than ECL or BiCMOS, taking only 13 mask levels to process a four layer metal H-GaAs III wafer. Vitesse reckons it outpaces ECL to match price-performance of BiCMOS and plans the first parts this year.
