Valid Logic Systems Inc and Epic Design Technology Inc have announced an agreement under which Valid has invested in Epic for a minority equity position. Valid and Epic will integrate Epic’s TimeMill timing simulator into the Valid environment and Valid will market and sell the product as part of its integrated circuit design product line. Joseph Prang, Valid’s marketing vice president, who will be Valid’s representative on the Epic board, says that by acquiring an equity position in Epic, Valid established a close, long-term relationship with an important partner, and strengthened its product line. In return, Epic receives the resources necessary to grow the company, and gains access to a worldwide sales and marketing organization. TimeMill is a mixed-level timing simulator and critical path analyser that can handle designs at the behaviorial, gate and transistor switch levels. Its delay calculation, based on post layout extracted data, has an analysis speed claimed to be around 10,000 times faster than Spice. The mixed-level capability supports a hierarchical design methodology, like Valid’s Scald methodology, in which components with different levels of abstraction can be mixed to achieve high efficiency simulation and verification. TimeMill also includes a critical path analyser which performs pattern-independent static path analysis and will run on all three machine families supported by Valid Logic – Sun, DEC VAX, and Valid’s own Scaldsystem. Product availability and pricing are due to be announced later this month.
