Privately-held Massachusetts Institute of Technology Lincoln Labs spin-out Integrated Computing Engines Inc, which recently moved to Waltham, Massachusetts, now expects to begin deliveries of its 32- or 64-way parallel Desktop RealTime Engine in the second quarter of next year. The Engine, which is the size of a small briefcase, is the first implementation of Computing Engines’s MeshSP interconnect architecture developed at the Massachusetts Institute of Technology and designed specifically to work with the 40MHz Analog Devices Inc ADSP-21060 Super Harvard Architecture Computer or Sharc signal processor. It supports EISA/PCI Digital Unix, Windows NT and NT hosts, with Irix and Mac OS support expected soon. Integrated Computing Engines will target high-performance graphics, signal processing and electronic design automation customers for the system, which is now in beta test at AT&T Co, Boston-based Onyx Sciences Corp, the Institute of Technology and others. It costs $100,000 for a 64-way, 7.7GFLOPS box, or $13 per MFLOPS, and Integrated Computing Engines touts the system as a low-cost, high-performance, high-volume offering. A 32-way system costs $50,000 and the company looks to sell hundreds. Computing Engines has already demonstrated ray-tracing and tomographic applications and will have the system on show at the forthcoming Supercomputing ’95 show in San Diego.
Sales in the hundreds
As Sharc becomes more widely adopted, Computing Engines investors including Sega Enterprises Ltd Corp minority shareholder CSK Corp and Cambridge Technology Enterprises Inc expect economies of scale to cut the system costs in half within a couple of years. Integrated Computing Engines claims four unidentified independent software vendors with a total of 1.5m users will move to MeshSP. The 25-strong company will sell direct initially, but is also seeking OEM customers. Integrated Computing Engines’s London office will handle European sales and a Japanese distributor has been lined up. MeshSP, a two-dimensional, toroidal shared memory model, connects each ‘slave’ processor to its four nearest neighbours. Instructions are distributed to the array of slaves by a master CPU which is identical to each slave but with direct access to program (off-chip) memory and runs Integrated Computing Engines’s Mesh/OS. In small configurations one of the slaves, each with up to 32Mb static RAM, can be provided with external memory and serve as a master and a slave. The unit’s serial 80Mbps input-output module (320Mbps if the serial ports of each slave are parallelised) connects the array to a host system, currently a Digital Unix, Windows NT or OS/2 system, with support for Silicon Graphics Inc Irix and Mac OS expected to follow. The host provides MeshSP access to peripherals, including console, networking and disk storage. Integrated Computing Engines claims the SIMD single instruction stream, multiple data streams MeshSP will also operate in SPMS single program, multiple data, or MIMD multiple instruction stream, multiple data streams modes, or in a combination of the three. The C-based programming model is converted to calls and instructions by the MeshOS. Host-based development tools include a SimSP simulator which can execute MeshSP code written in C to examine parallelising issues. SimSP is compatible with ANSI C compilers and debuggers. LibSP is a collection of MeshSP routine and services; ViewEDM is a window display system; LibSIMD is a modified ANSI C library for Sharc/SIMD; ICEsuite is a GNU C compiler, linker, assembler, and IBM debugger; RulesSP are described as parallel productivity tools; there are also other C/C++ compilers and assemblers for Sharc. An ICEstart package includes personal computer server, MeshSP test hardware and software tools.