IBM revealed a few details of the new RISC processor to be used in the forthcoming successors to its RT Unix line at last week’s Microprocessor Forum in San Jose last week. According to Microbytes Daily, the company said that the chip would include integrated 64-bit floating point and 32-bit integer arithmetic, and branch processing units, with more overlap in the operation of the three, so that as many as three instruction words may be issued per cycle where the software is able to detect parallelism.It will have separate data and instruction caches, with 64-bit and 128-bit interfaces, for a memory bandwidth of up to 400M-bytes per second. The set has been implemented in 1 micron CMOS with parts having densities of 300,000 to 1m devices per chip. IBM also commits to doubling performance every 12 to 15 months and says the press will be very surprised at what we’ve got.
