Unisys Corp has been lifting the curtain a little on its plans for the Unix-based U6000 range, most interesting of which will turn up in a forthcoming U6000/500, the flagship design on which future distributed processing systems will be based. According to today’s issue of our sister paper, Unigram.X, the 500 will feature up to five processors and a high performance memory bus. In this machine, some of the work Unisys has been carrying out with academic partners such as the California Institute of Technology and the Jet Propulsion Laboratory in Pasadena, and with French microkernel specialist Chorus Systemes SA, will come to light for the first time. With its partners, Unisys has been working on five-by-five Hypercube hubs using Intel Corp iAPX-86 microrpocessors, which can be clustered together, either in-cabinet or externally, connected through the Jet Lab’s Hyperswitch firmware, and front-ended by a serial fibre optic link. The operating system to hold it all together as an applicationtransparent, single system image, is the Chorus V.4-compatible micro-kernel-based system, on top of the ISIS message broadcasting algorithms from Cornell University. It is essential, the company says, to be able to hook in both symmetrical multi-processors and distributed processors into the same system. With 320 processors, such a distributed system could reach TPC-A performance approaching 25,000tps, Unisys Unix chief Ronald Bell estimates. There is a problem with high processor counts, he says. Compute performance is increasing by 1.7 times every year, while bus bandwidth is going up by only 1.3 times. So we are having to look at distributed processing. Unisys doesn’t regret its decision to eschew RISC and stick with Intel, and is making sure its products are enabled for multiple levels of Intel chips, in cluding the P6, which Intel says will be ready by the end of next year. That, he says, will feature all the attributes of RISC anyway.
