Synopsys’s memory IP development environment solution will feature three components that contribute to reducing development time. It will also feature an integrated memory quality assurance (QA) system source code for all standard memory architectures and characterization utilities.
The integrated memory QA system will reduce development time by enabling production-ready memory releases. The characterization utilities ensure the generation of memory models.
Raymond Leung, vice president of memory IP development at UMC, said: As part of UMC’s SoC foundry solution strategy, we are seeking to further enhance our portfolio of memory IP in order to meet our customers’ ever-expanding requirements as they design into today’s most advanced technologies. Synopsys’ memory development automation environment is capable of developing memory IP solutions for 65nm and 45nm memories and cores. The combination of Synopsys’ development environment, support and training, makes this a valuable EDA offering for meeting our customers’ memory IP requirements.
