Underlining how seriously it takes Rambus Inc’s new technique for increasing the speed of processor access to memory 10-fold (CI No 1,878, 1,880), Toshiba Corp says that it has already developed a 4M-bit dynamic memory chip using the Mountain View, California company’s technology, and says that it will start sample shipments in October. Using a 0.7 micron design rule and Rambus technology, Toshiba’s high-speed 4M-bit dynamic actually 4.5M-bits – delivers data at 500M-bytes per second, compared with 100M-bytes per second for a standard dynamic downloading to a 32-bit bus. It also achieves an access time of 2nS compared with the 55nS to 80nS typical of conventional parts. Toshiba says it is also developing a 16M-bit Rambus DRAM, for introduction in 1993 and that it initially plans to use the technology in laptops to provide high graphics performance. The Rambus system replaces the control signals and multiplexed address of a conventional RAM with a packet-oriented bus, and Microprocessor Report notes that the founders of the company were key participants in the design of the R6000-based ECL systems at MIPS Computer Systems Inc, and that the Rambus is based on the system bus used in MIPS’ RC6280. The Rambus Channel operates with a 250MHz clock, transferring a 9-bit byte at each extremity of the clock cycle – or one every 2nS. There are no address lines – instead, addressing is performed by packets transmitted on the data lines. Although for maximum performance, the microprocessor should have the Rambus interface designed in, early designs are expected to use an application-specific circuit that translates the microprocessor’s native bus to the Rambus protocol. Fujitsu and NEC have, as reported, also licensed the Rambus technology and Fujitsu is expected to provide Rambus support for its Sparc microprocessors, and NEC is to develop an R4000-to-Rambus interface chip.
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