Cadence Design Systems Inc and Toshiba Corp have been working together to design and develop a system chip using the reusable intellectual property standards set down early this year by the Virtual Socket Interface Alliance (CI No 3,089). The Alliance aims to help chip makers share reusable chip components and then add value to create a single system on a chip, and Toshiba is the first large company to launch products using the standards. Engineering teams from Cadence and Toshiba have collaborated on designing Toshiba’s TX19 32-bit RISC microprocessor core to make it compliant with other Virtual Socket Interface components, so that various manufacturers can use the microprocessor as part of their own system on a chip designs. Toshiba and Cadence also worked together to develop a microcontroller, which takes the TX19 core and adds 14 additional reusable intellectual property, or IP blocks. The core will be offered to Toshiba customers so that they can integrate it with other IP blocks. The companies say Cadence also ensured the blocks were designed in such as way as to be readily reusable throughout Toshiba. The TX19 core itself was assembled from existing Toshiba IP blocks. The 14 blocks added to the core for the microcontroller include things like Parallel I/O, DRAM Control, External Bus Interface, a Debug Support Unit and a Clock Generator. The resulting 3.3 volt microcontroller, optimised for 0.35 micron manufacturing, can accept either 16-bit or 32-bit instruction sets, enabling designers to reduce the amount of external memory needed for control code storage by using 16-bits if required. The number of system level integrated circuits is predicted to grow substantially over the next five years, and Cadence’s new chief executive, Jack Harding (CI No 3,273), says they will enable development of new, feature rich devices that will open up vast new horizons for electronics. Other large companies are expected to announce Virtual Socket Interfaces over the next few weeks.
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