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February 28, 1994

TOSHIBA HAS NEW SINGLE CHIP VIDEO DECODER TECHNOLOGY

By CBR Staff Writer

Toshiba Corp says it has developed a single-chip video decoder that meets the MPEG2 standard and can decode compressed digital signals with high definition television-level image resolution. The chip reconstructs a moving picture from compressed data and can reproduce a real-time, HDTV-quality picture from a 1,152 by 1,024-line by 30 frames-per-second HDTV digital signal. The decoder is fabricated in a single-chip 0.5 micron triple-level-metal CMOS structure and integrates 1.1m transistors on a 15mm by 15mm chip. With four peripheral 4M-bit memory chips, it is claimed to decode standard NTSC-quality signals at 3.3V. Provision of high-speed synchronous DRAMs and the device’s 70MHz clock speed assure the access speed required for an HDTV-quality digital signal, Toshiba says. The chip’s inverse discrete cosine transform processor macrocell and variable length decoder macrocell have both been newly developed in order to support HDTV signal decompression. Among other technical advances, parallel decoding in the variable length decoder and the built-in RISC microprocessor enables both to decode data bit streams at the same time, providing the processing speed required for information-rich signals. This avoids conflicts and speeds operation. Toshiba plans to integrate the new chip in a range of application specific chips that will be introduced starting second half 1994. No prices were given.

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