Toshiba has developed circuit techniques for embedded SRAM that operate in a wide supply voltage range, from 0.5V to 1.0V, that contribute to lower power consumption by electronic devices, it was reported.
It is said that the test chip fabricated uses three new techniques to facilitate proper operation of SRAM even when there is variation in operating voltage. It also manages to ensure that the failure rate is reduced and fast operation is achieved.
The company is said to have demonstrated these techniques in a 40nm 2Mb SRAM test chip at 0.5V operation.
Toshiba’s new circuit technique predicts SRAM cell failure rate in real time and automatically programs wordline voltage so that the cell memory is retained even when operating conditions vary.
The result is a reduction in the cell failure rate to one-hundredth that of conventional SRAM. This new circuit technique also eliminates the need to program the wordline level voltage chip by chip, which conventional SRAM require, it is said.
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