Where will the Workplace microkernel appear first? Which machine will get the most powerful PowerPC processors first? The new parallel RS/6000s? No. The SP2? No. In fact, the PowerPC 630 will bow in IBM’s AS/400. IBM Corp’s Rochester division is one of the most technologically hungry operations around. If things go to plan, within a couple of years the AS/400 will be transformed into a catch-all machine, capable of running Unix and OS/2 applications and Taligent frameworks alongside its traditional OS/400 programs. That’s all thanks to a software strategy based around the Workplace microkernel. At the same time the division is hoping to broaden the spread of applications through an increase in processing power – hitherto, the sensible user has not tried to use the AS/400 for processor-intensive work. Such was Rochester’s impatience for high-end PowerPC processors that it has been forced to design its own variants. Rochester’s silicon had its first outing with the resurrection of the System/36. The new box provides the Rochester labs with a dry run for the PowerPC AS/400 proper. The machine’s single-chip processor is a Rochester-designed 64-bit device that can almost, but not quite, be called a PowerPC. The only reason it cannot is that it runs only in 64-bit mode and cannot be switched to run as a 32-bit device, according to Frank Soltis, the AS/400’s Senior Engineer and Scientist. Virtually stall-proof Soltis says that while the processor shares some common technology with the PowerPC 620, it cannot really be called a variant. Next summer the chip will be modified to incorporate a 32-bit/64-bit switch and it will become a true PowerPC processor. This will be used in the System/36 but also in a low-end AS/400. At the same time, a high-end RISC AS/400 will be launched using the multi-chip implementation of the PowerPC 630. We wanted the 630 architecture and could not wait for the single chip, he said. Rochester’s proto-630 uses seven chips. All the execution units together with an instruction cache are bundled onto the first. The floating point unit gets chip two to itself, while chips three, four, five and six provide 256Kb of data cache. The final part handles input-output. Details of exactly how many execution units are present were not to hand, but Soltis says the multi-chip implementation can dispatch four instructions per cycle and up to 13 instructions can be executing concurrently. This disparity between maximum number of instructions dispatched and maximum executing sounds a little odd, but if right, this will be a very highly scaled processor which should be virtually stall-proof. In order to compensate for the comparatively sluggish inter-chip connections, the AS/400 unit is fabricating the multi-chip module in BiCMOS. However the proper single chip 630 will be fabricated in the cheaper and slower CMOS like the rest of the PowerPC family. The aim is to complete this during 1996. Whether the finished 630 will actually squeeze down onto a single chip is still moot. There is a possibility that it will end up with the cache on a separate piece of silicon to the rest of the processing units. In a departure from the PowerPC norm, the 630 contains extra instructions, requested by IBM’s RS/6000 and AS/400 divisions. So, according to Soltis, it contains special hooks for interfacing with matrix-manipulation processors, as requested by the RS/6000 division. Meanwhile the AS/400 developers asked for, and got, special memory-addressing modes, string manipulation and decimal arithmetic. The PowerPC 630 started life as the Power3 architecture, and was subsequently handed over to the Somerset joint design lab. The inclusion of IBM-specific (and possibly undocumented) instructions into the 630 looks a little strange in the context of promoting PowerPC as a vendor-neutral processor standard. Indeed, Soltis admits that Motorola Inc is currently muttering that it doesn’t really want matrix-manipulation hooks and the like. However, he says that the extra functions take up very little extra silicon real estate and that by the t
ime the chip comes out, Motorola and Apple Computer Inc might be grateful for the extra facilities. By Chris Rose Meantime, Soltis says, the multi-chip part is currently sampling and running in the labs at 200MHz. Initially, it will be driven at a lower clock speed, giving IBM some headroom for performance expansion – expect next year’s AS/400s to run at something like 150MHz or 166MHz. The division has set itself ambitious performance targets: Over the next three years we will take systems [to] over five times their present limits says Soltis. If the AS/400 division was purely interested in running native System/36 and AS/400 applications, it would have no interest in a 32-bit mode, since both machines’ operating systems are now pure 64-bit affairs. The primary benefit of 32-bit working is the ability to run OS/2 on the PowerPC and AIX on the AS/400’s main processor. The AS/400 division is nearing completion of an extensive rewrite of its OS/400 operating system. Included in the work is a redevelopment of the machine’s Licensed Internal Code, the lowest layer of software. As a result, the AS/400 software architecture now looks very similar to the good old Workplace-plus personalities model. OS/400 is a personality running on a Mach-type microkernel. Soltis admits that it isn’t quite the full Workplace yet, but that hasn’t stopped enthusiastic Rochester inhabitants telling users that we will have Workplace before the PC guys in customer briefings. More work will need to be done before OS/2 and OS/400 will run side-by-side. Though the final goal is to have AIX and OS/2 running as Personalities on the main processor, Rochester has constructed a contingency plan. It is just as well, since the AIX guys are taking what can best be described as a leisurely approach to building an AIX personality for Workplace. When Rochester has switched to PowerPCs from 68020s for the vast array of input-output processors in a large AS/400, it will be able to use these input-output chips as full co-processors hosting other operating systems. This approach has already been tried and tested. Back in May the company announced the File Server input-output processor, an iAPX86 chip destined to sit inside the AS/400 and run OS/2 LAN Network Manager. The idea is for the machine to provide OS/2 server support transparently. Accusations There wouldn’t be much point in running OS/2 server applications on the AS/400 if the two operating systems could not share and access each other’s data. This too was tackled in May with the launch of the new High Performance File System, which changed the AS/400’s disk system to make it compatible with OS/2. Soltis recalls accusations at the time that the company was degrading the AS/400 disk handling to make it fit in with the personal computer operating system. In fact, it was the other way around, he says: the native AS/400 file system turned out to be a perfect subset of the OS/2 scheme – pure serendipity, he says. So the Personal Software Products division has an unexpected ally – the AS/400 Division is actively courting developers to convince them to convert applications for OS/2. Lotus Development Corp is already implementing Notes according to Soltis, so expect to see the AS/400 become a Notes server sometime next year. And then there is AIX. How will an AS/400 based on a Peripheral Component Interconnect bus and running AIX differ from an RS/6000? IBM is going to have to be careful to keep the two machines from overlapping their markets, particularly since on the other side of the equation, the RS/6000 is being increasingly touted as a business machine. Soltis says that his division will be steering clear of the RS/6000 heartland. Instead, the ability to run AIX will be played as a method for integrating AS/400s into larger sites. It should also remove some of the nasty taste left by the word proprietary in the mouths of potential AS/400 purchasers.(C) PowerPC News, available free by mailing add (AT SIGN) power.globalnews.com.
