MIPS Technologies Inc and Toshiba Corp brought forward by a couple of weeks the announcement of the TFP version of the R-series RISC, which is now called the R8000 (CI No 2,431). The two-chip set – it has a superscalar integer and a dual floating point units – is rated at 310 SPECfp92, taking the record away from IBM Corp’s Power RISC, and 108 SPECint92. Manufactured in 0.5 micron, three-layer metal CMOS technology, it’s the first implementation of the MIPS IV instruction set and issues four instructions per clock cycle. MIPS’ parent Silicon Graphics Inc has been discussing the floating-point-intensive, symmetric multiprocessing-enabled TFP since April 1992 and it was originally expected by the end of 1993. The part is destined immediately for Silicon Graphics’s TFP-ready Power Challenge servers which have been awaiting the processor. The firm says a two-way with R8000 will do 449 double-precision 1,000 by 1,000 Linpack MFLOPS, 767 as a quad system and 1,177 as an eight-way. Power Challenge servers go up to 16 CPUs. The partners now say that the chip, being fabricated by Toshiba Corp, is 24% more powerful than expected. It will cost $2,000.
