Texas Instruments (TI) has unveiled a new System-on-a-Chip (SoC) architecture based on its multicore digital signal processors (DSPs) that integrates fixed and floating point capabilities in CPU.
The company said that the new multicore SoCs offer up to 1.2GHz and provides an engine with up to 256 GMACS and 128 GFLOPS, and offer vendors a common platform to accelerate the development of infrastructure products such as wireless base stations, media gateways and video infrastructure equipment.
The new SoCs integrate fixed and floating point processing within each DSP core; and a suite of tools, software libraries and platform software enabling faster development cycles and effective debug and analysis, TI said.
According to TI, the product family includes a range of devices starting with four-core device for wireless base stations, eight-core device for media gateway and networking applications and layer 1, layer 2 and network co-processors. The direct communication between cores and memory access with multicore navigator frees peripheral access.
The company claims that the TeraNet 2, a 2 terabit per second on-chip switch fabric, provides high bandwidth and low latency interconnection of all SoC elements. In addition, the multicore shared memory controller allows faster on-chip and external memory access.
Brian Glinsman, general manager of communications infrastructure business at TI, said: With this new multicore architecture, we challenged ourselves to exceed Moore’s Law by bucking the trend of simply linearly increasing the amount of cores on each platform; instead, we increased overall performance with significant enhancements to the DSP, a new breed of coprocessors, and reduced power consumption.
