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Technology / AI and automation


Over the past few years, tying lots of processors together to work in parallel has become an accepted way of getting supercomputer performance for a relatively modest outlay, and one of the major growth areas for Unix. There are many possible ways to connect the processors to each other and to memory, input-output subsystem and peripherals. The CPUs can talk directly to each other; to a number of neighbours in an array; communicate via a region of shared memory; or via a control processor that also loads instructions and data into each processor. However, as the number of processors and devices to be connected grows, the problem of interconnecting them grows too. The perfect solution has always been the crossbar switch, which bi-directionally links every port with every other port (it was developed for telephone exchanges, which is why any phone can connect to any other phone in the world – crossbar switches in every exchange) but they have always been too expensive for anything except a few top-end mainframe computers. But Texas Instruments has now brought out a 16-port crossbar integrated circuit that acts as a dynamically reconfigurable, non-blocking interconnecting network for parallel computing systems. It allows multiple microprocessors, or other processors such as array processors, accumulators, co-processors, or multipliers, to work simultaneously in small systems with full bidirectionality. Each of the chip’s 16 input-output ports can be independently controlled to allow any two processors or peripherals to exchange data or instructions without interfering with any of the other data paths, thanks to an internal 64- bit data bus (each port handles 4 bits at a time). The ports can be ganged together to handle 16 4-bit, eight 8-bit, four 16-bit or two 32-bit data paths, and several of the chips – the part is called the AS8840 – can be operated in parallel by connecting their control units in parallel. Each port can be set in one of two ways; when the control signal is high, data is passed directly to the internal 64-bit data bus and on to another port; when the control signal is low, the data can be sent to either or both parts of a two-part 64-bit memory built up to two groups of eight 4-bit register latches.

Simple fault-tolerant system

The buffered data from either or both parts of the memory can be stored and forwarded to any port, even the one it came from. Users can control this and any other operation either with control signals from a master supervisor or with control signals embedded in the processor data flow. The circuit is divided into two parts around the 16-by-4-bit data bus, with eight ports on each side. This allows a processor sending out data to receive it again when it has passed through the network to ensure that no errors have crept in – and automatic rerouting on fault detection would allow a relatively simple fault-tolerant system to be designed. Also, the ability to select externally between two different data sets in the two parts of the memory allows the same data to undergo two different permutations without reloading – useful for operations such as fast Fourier transforms. And the two-part register latch memory allows loop-back functions – data can either enter or by-pass the registers and loop back to the input – very useful for sorting operations. The 8840 crossbars can be linked together to provide a number of different topologies: for example, just two are needed to provide the switching for a ring topology. One switch or ring connects a number of processors to a bank of shared memories, while the other ring links printers, terminals, hard disk units and back-up memory. When the two rings are connected by two 4-bit expansion lines, all the processors, memories and peripherals are directly connected to each other. And by using larger buses, even more crossbar chips can be connected together to link more and more units together.

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CBR Staff Writer

CBR Online legacy content.