Teraplex Inc, the intriguing Champaign, Illinois company formed to exploit a technology that goes one step beyond RISC – Minimum Instruction Set Computing (CI No 1,462) – has been shedding a little more light on the concept. Its 65MHz microprocessor will have fewer than 20 instructions, mainly computational operations which are executed by a universal functional unit comprising adder, high-speed proprietary multiplier, logic switch, floating point unpacker and floating point packer. No instruction decoding is needed because the instructions include all the control information needed for their execution. Despite the atomic nature of the instructions, the processor uses a very long instruction word of 128 bits to improve bus efficiency by enabling the transfer of multiple addresses and operands in a single bus cycle – but it does require more memory than RISC or complex parts to operate at maximum efficiency. The key benefit claimed for the technology is that the instructions are so low-level that they can be combined to mimic any proprietary instruction set. Just as companies like Micro Focus Plc have their compilers compile down to an intermediate code that is then interpreted, so that to implement the compiler on a new hardware architecture requires only writing a machine-specific interpreter to slip in under the universal compiler, so with the Teraplex architecture, any processor instruction set can be emulated simply by writing an instruction stream decoder that aggregates the atomic instructions to create each instruction in the proprietary set so that microcode is replaced by software. The Teraplex compiler will take the high-level language code and compile it down to the Teraplex Intermediate Language Interface. The Intermediate Language assembly language then compiles the instructions down to the atomic instructions. The company is currently working on an 80386 emulation for the processor, which it calls the MISChip, and says that the part executes 80386 code 4.5 times faster than a 33MHz 80386; for comparison, RDI Computing Inc says that its software emulation of the Intel Corp architecture for the Sparc chip delivers MS-DOS performance equivalent to the 80286 (CI No 1,625). As reported, Teraplex has signed Atmel Corp to fabricate the MISChip, but is backing off from its second quarter target launch date. It plans to put the Teraplex Intermediate Language Interface into the public domain to encourage third parties to develop software.
