Seattle, Washington-based Tera Computer Co says its MTA shared memory Multi-Threading Architecture supercomputer will be announced in a couple of months. Tera, which late last year signed Unisys Corp to build its machines under contract (CI No 2,809), says it is currently working with a final prototype of the shared memory massively parallel system and expects no more design changes to be made. Multi-Threading Architecture will use from six to 256 CPUs of Tera’s own design, each of which will be able to process up to 128 threads, or pieces of an application at a time using automatic parallelising compilers. The chips perform three instructions per clock cycle. Because memory is shared, Tera says its cache-less design will eliminate memory latency and locality issues. And additional processors can added without limiting performance. It claims Multi-Threading Architecture, which runs a version of BSD 4.4 Unix, will run Cray Research Inc vector application supercomputer code with normal porting. MTA systems will be priced from $10m in the third quarter, but it has got no advance customers for the thing. Tera will be taking Maximum Strategy Inc’s Gen5 XL storage servers OEM for use with Multi-Threading Architecture. It has already got PsiTech Inc, Fountain Valley, California, developing client and server versions of its OpenGL and X software for use with MTA. Tera is also to resell PsiTech’s HIPPI-attached frame buffers designed to be used in conjunction with PsiTech’s displays. Trea was formed in 1987 to deliver the world’s most powerful supercomputer system in 1993 (CI No 1,215).
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