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April 15, 1997updated 05 Sep 2016 12:34pm

TERA GOES TO CADENCE FOR HELP WITH CMOS SUPERCOMPUTER CHIP

By CBR Staff Writer

Tera Computer Co, the Seattle, Washington-based supercomputer company which has only just brought its MTA Multithreaded Architecture systems to market after a ten year development effort (CI No 3,131), has gone to Cadence Design Systems Inc to help it implement its central processing unit in CMOS technology. Tera will pay San Jose, California-based Cadence $8m to help it develop the microprocessor, which it will use for future systems containing thousands of processors. Tera currently goes to Unisys Corp to manufacture its custom designed gallium arsenide CPU, and the many application specific integrated circuits that support it. Early versions of the Tera design were uniprocessors, but the first system it has sold, to the San Diego Supercomputer Center, is an eight processor system, and the current machine could scale up to 256 processors, according to Tera’s president and chief executive officer Jim Rottsolk. The new machine will use the same architecture, and retain the feature Tera feels gives it its advantage over rivals, unified shared memory. The big problem with shared memory is memory latency, said Rottsolk. We don’t avoid latency, we tolerate it. Each single processor has within it 128 virtual processors and register sets, giving a high degree of parallelization even on single processor systems. The CMOS implementation will help lower cost and CPU footprint, and will give Tera a wider choice of manufacturers. Cadence, historically a tools company, has been moving into the design services business over the last few years, and Tera has already been working closely with the company on its current processor.

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