Electronic Design Automation industry Synopsys and network-on-chip (NoC) interconnect IP applications supplier Arteris have launched joint analogue and digital IP applications to implement the MIPI Alliance Low Latency Interface (LLI) 1.0 specification.
Arteris and Synopsys give system-on-chip (SoC) designers access to pre-tested and pre-optimised analogue and digital MIPI-based IP by providing a collaborative application that adheres to the LLI specification.
The joint application consists of Arteris’ Flex LLI MIPI LLI digital controller IP and Synopsys’ DesignWare MIPI M-PHY IP.
The joint application’s functionality and interoperability was validated by a team of Arteris and Synopsys engineers, which was formed to facilitate its verification and testing.. .
The LLI specification utilises the MIPI M-PHY physical layer, which also supports five other protocols including USB SSIC, JEDEC UFS, MIPI CSI-3, DSI-2 and DigRF v4.
The round-trip latency of the LLI inter-chip connection speed enables a mobile phone modem to share an application processor’s memory while maintaining enough read throughput and low latency for cache refills.
MIPI Alliance Board chairman Joel Huloux said Synopsys and Arteris are aiding in the adoption of the MIPI M-PHY and MIPI Low Latency Interface.
"The early integration and availability of the Arteris and Synopsys solution helps speed time to market for MIPI LLI adopters," said Huloux.
