UltraSparc-I – Sun Microsystems Inc’s 64-bit Sparc implementation (CI No 2,127) is intended to carry the Sparc RISC design into the realm of 140MHz to 200MHz clock speeds, producing chips that measure between 220 and 300 Specint 92 and between 350 and 500 Specfp 92. First silicon of the follow-on UltraSparc-II a year later should start where UltraSparc-I leaves off, going to 275MHz with Specint 92 ratings of between 325 and 475 and Specfp 92 between 550 and 750. The earliest UltraSparc-III silicon is scheduled for the fourth quarter of 1996. The UltraSparc-III will break with the 0.5-micron CMOS technology of its predecessors and use 0.5/0.4-micron BiCMOS techniques instead. Like all of Sun’s chips, UltraSparcs will be manufactured by one or more of its semiconductor partners.
Flaws
Texas Instruments Inc is a likely choice. The chips, offering upwards binary compatibility with preceding generations, will adhere to the Sparc V9 specification that was published by the Sparc International supporters club last year. Sun intends that the UltraSparc should be highly superscalar and to handle four instructions in each clock cycle. It will include dual-launch floating point units and be made out of a four-level metal process. Scalability issues have dogged the 32-bit SuperSparc, Sun’s current high-end microprocessor. Design flaws made it hard to manufacture the thing in volume at 40MHz until recently, although it was originally targeted at high clock rates. Despite these serious hiccups, Sun maintains the continued scalability of Sparc and claims that simulations prove the viability of the UltraSparc. As a result of changes in the original masks, Sun now speaks of a SuperSparc and a SuperSparc+. The former is the result of its initial work and produces its current 33MHz and 40MHz Viking iterations. The SuperSparc+, producing early silicon now, will take it from 45MHz to an anticipated 60MHz in the fourth quarter. (Sun says that it is getting 50MHz parts now.) In the first quarter of 1994, a SuperSparc-II kicks in with first silicon clocked at around 65MHz and by the fourth quarter it should be up to 90MHz. Systems introductions will of course lag all silicon by some months. The 0.7-micron SuperSparc+ should benchmark from about 75 to 100 Specint 92 and from 108 to 135 Specfp 92.
The microprocessor wars are going to get vicious over the next two or three years, and to convince its acolytes that Sparc will be one of the survivors, Sun Microsystems has been mapping out the future of the architecture. Maureen O’Gara has been right there listening.
The SuperSparc-II will move to a 0.6-micron technology and Sun will add an enhanced integer unit, new floating point and dual-launch floating point. When they are combined, these enhancements are expected to increase the SuperSparc-II’s floating point to a integer ratio. It should benchmark at between 115 and 150 Specint 92 and between 162 and 200 Specfp 92. Texas Instruments will manufacture the new SuperSparcs as it does the current ones. All SuperSparcs will follow the older 32-bit V8 specification. These multiprocessors will do three instructions per cycle and will be fabricated in a three-level metal process. Sun is also developing multiple iterations of Tsunami, its low-end low-cost high-volume single-chip MicroSparc engine. Sun could move the manufacture of these parts from Texas Instruments, which began it quite successfully, to Fujitsu Ltd, which has been very anxious for the business. Sun figures that it could have 75MHz versions of its current MicroSparc by the summer. By the end of the year, it should have early silicon on the MicroSparc-II part, which is designed to go from 70MHz to 100MHz by the fourth quarter of 1994. MicroSparc-II will get a new floating point unit, an enhanced integer unit, 4x cache and power management. Manufacture will move from a 0.8-micron process to 0.5 micron and from a two-level metal to a three-level. Voltage will shrink from 5 Volts to 3.3V. It should come in at around 45 Specint 92 and top out at around 60. The sketchier MicroSparc-III, expe
cted to produce silicon in early 1995, will pick up at 100MHz and go to 125MHz by the beginning of 1996. It will use faster transistors and an external cache. All MicroSparcs are uniprocessors capable of one instruction per cycle, and again follow the 32-bit Sparc V8 guidelines. Sun reckons that its only competitors are Intel Corp and the IBM Corp-Motorola Inc-Apple Computer Inc PowerPC. In fact it figures that these two architectures plus its own will be the only survivors of the coming silicon shoot-out.
Vapourchip
To ensure its place, it is wading into the vapourchip fray from what it claims is a more defensible position. Its products are more seamless and easier to work with because its compilers and operating system are factored into the design. It wrings higher performance per clock than anybody and it has not broken compatibility the way Intel intends to do with the P6 and the way IBM has done with the Rios and its subset, the PowerPC, having apparently failed to scale the thing down to the desktop and having instead been forced to strip out 40 instructions and substitute a software emulator.
