Sun Microsystems Inc will reveal the first design details of its proposed first MAJC processor at the Microprocessor Forum today (Wednesday). The MAJC 500 convergence processor which is designed to handle the real-time flow of multimedia data, will integrate two 128-bit very long instruction word processors onto a single piece of silicon. MAJC Chief architect Marc Tremblay will detail the chip at the conference.
MAJC, which Computerwire first revealed as a project within Sun back in June, and which Sun eventually announced in August (CI No 3,684; 3,716), is a new architecture that Sun says will be capable of processing the real-time streams of visual and audio information needed by an emerging set of new multimedia applications. It will be easily programmable from current high- level languages – including Java – and combines both multi- threading and multi-processor approaches, for scalability across generations of applications, older and newer.
Simulated benchmarks carried out by Sun are said to show that the MAJC 5200 will be capable of decoding two MPEG streams in real time while simultaneously doing a surround sound audio decode or a web browsing session. In Sun’s example, a user could simultaneously view two different television programs delivering finance and news while interacting with a web site to buy new business equipment.
The MAJC 5200 is expected to be able to handle over one hundred voice-over-IP channels while enabling encryption and decompression of the packets over a 10 gigabit-per-second Ethernet connection – so that large numbers of simultaneous phone conversations could be supported in a small-footprint gateway server device. Sun has also simulated the performance of the chip running Java, image processing, networked video, H.263 teleconferencing and advanced audio applications in real-time. Raw performance has been quoted as 6.16 GFlops single-precision, 1.5GFlops double-precision. Graphics performance varies from 62 to 92 millions of triangles per second, depending on the complexity of the shading.
The first MAJC 5200 chip is expected to use .22 micron, six layer copper process and have a clock frequency of 500 MHz. It will consume 15W of power and come on a die size of 220m. The 5200 is expected to tape out by the end of this year. Engineering samples are expected in the second quarter of 2000. Further out, MAJC- 5200+ will move to .18 micron seven layer copper technology and have a clock speed of 700MHz at the same power consumption.
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