Sun Microsystems Inc [SUNW], which eagerly wants to get its dual-core UltraSparc-IV into production early in 2004, will use the event to tell people a little more about this chip and why Sun’s giant Unix server customer base should get their budget dollars in order for this forthcoming chip.
The UltraSparc-IV, which is code-named Jaguar, is essentially two Cheetah UltraSparc-III cores jammed onto a single piece of silicon. Before getting into the specifics of the chip, it is important to clear up an important misconception about the UltraSparc-IV chip.
The UltraSparc-IV is not pin compatible with the UltraSparc-III. Although it uses the same physical packaging and, thanks to an improved 130 nanometer copper/low-k dielectric process created by Sun’s chip partner, Texas Instruments [TXN], can be jammed in about the same space, the Jaguar chip has a few pins that cope with signals from system boards that tell it how to route data and processing requests to specific chips.
What this means is that UltraSparc-IV processors will be put into new system boards that can be plugged into existing Sun Fire V480, V880, V1280 V-class frames or in the Sun Fire 3800, 4800, 6800, 12000, or 15000 servers, which have their own boards as well.
You will not be able to pop out an UltraSparc-III processor in an existing system and pop in an UltraSparc-IV to boost the performance of your machine – as many of us were under the impression could happen. You’ll have to do a system board upgrade, instead.
Sun will use Microprocessor Forum to explain that the first generation UltraSparc-IV processor will use the same 130-nanometer process from TI that Sun will use in its dual-core Gemini processor. Gemini, as Sun explained at the Hot Chips conference in August, is based on the cut-down UltraSparc-II Blackbird cores, not the UltraSparc-III or Jalapeno UltraSparc-IIIi cores. It’s back to the future.
The Gemini chip is sampling at 1GHz and 1.2GHz clock speeds now and dissipates only 32 watts of power at the faster clock speed. The Gemini chip will support one thread per core and four instructions per thread, for a total of eight simultaneous instructions per chip.
The chip will obviously be binary compatible with the other Sparc processors and will include new RAS features and error correction electronics. The Gemini chip will have an integrated DDR1 main memory controller and a JBus system bus interface, just like the Jalapeno chip. The Gemini chips will run at between 1GHz and 1.2GHz initially, and will be pin compatible with the Jalapeno chips. A Gemini machine will be able to support one, two, or four of these dual-core processors.
The UltraSparc-IV processors will be initially offered at 1.2GHz using the 130 nanometer process from TI. It hasn’t been revealed yet how high the clock speed will go when the second-generation UltraSparc-IVs debut, sometime during the first half of 2005 using a 90 nanometer copper/low-k process that also adds strained silicon to shrink transistor sizes, but Sun should be able to easily hit 2GHz with the Jaguars, and maybe even 3GHz is possible if yields are good.
The eight-core Niagara processor Sun is working on for the 2005 timeframe for entry and midrange servers will use this same 90-nanometer process. And when TI perfects that process on Sun chips, it will make ka-gillions of DSPs and other specialized chips on 300mm wafers.
The first generation of UltraSparc-IV processors will have an on-chip main memory controller, just like the UltraSparc-IIIs, and 16MB off-chip L2 cache memory that is statically partitioned into two pieces, one for each core on the chip.
Sun has told customers they can expect a machine with the Jaguar chips to provide about twice the per-thread performance as a Cheetah chip, which stands to reason. I estimate that a Sun Fire 15000 with 72 UltraSparc-III processors running at 1.2GHz can crank through about 475,000 transactions per minute on the TPC-C online transaction processing benchmark test.
Doubling that to anywhere from 850,000 TPM to 950,000 TPM puts the StarCat back in the game against IBM Corp’s [IBM] Regatta and Hewlett-Packard Co’s [HPU] Superdome, and can even give Fujitsu-Siemens a run for the Unix money.
But soon after Sun announces the Jaguar chips, IBM will be rolling out its Power5 chips and Squadron servers, and HP will have dual-core PA-RISC and dual module Madison Itanium Superdomes out the door. Sun needs to hold parity on per-CPU performance with IBM, HP, and Fujitsu-Siemens for more than a few months to sustain its business because most enterprise software is priced based on CPU count.
That second generation Jaguar processor using the 90-nanometer technology will have more tweaks of the basic Cheetah core than the first generation Jaguars did. Specifically, says Sun, the L2 cache will be moved on chip – Sun won’t say, but a 4MB or 6MB L2 cache is a likely size – while a much larger L3 cache will be added off chip to further boost performance.
Sun is also going to increase the number of transistors dedicated to L2 memory tags by a factor of eight in the Jaguar kickers while shortening the cache line size from 512 bytelines to 128 bytelines. This should up the hit rate in the L2 cache, and therefore boost performance on workloads that are cache sensitive, like, say, Java applications.
With the second-generation Jaguar chips, Sun has a target of three-to-four-times the performance of current Sun Fire systems using the 1.2GHz UltraSparc-III chips. That puts a 72-way machine in the realm of 1.4 million to 1.9 million TPM.
In the 2005-2006 timeframe, TI will have a 65-nanometer process that will allow Sun to shrink its chips and crank-up the clocks even further on the UltraSparc-IV, if it needs to. And the same processes will be at the heart of the simplified, many cored designs that Sun has not even given a name to outside of the company as yet, but which are targeting a factor of 15- or 30-times the performance of Sun’s current low-power UltraSparc iSeries chips.
This article was based on material originally published by ComputerWire.
