Sign up for our newsletter
Technology / AI and automation

SUN MICROSYSTEMS “SETS 10 MIPS RISC FAMILY FOR JULY LAUNCH”

Sun Microsystems Inc now has 100 systems built around its own Reduced Instruction Set processor running in-house at Mountain View, California, and is planning to announce the first machines using the 32-bit chip set next month. So says Computer Systems News, adding that the set, initially clocked at 16.6MHz and rated at a racy 10 MIPS, is believed to have been designed using 1.5 micron Fujitsu semicustom arrays integrating 15,000 gates per chip, and may be passed to Cypress Semiconductor, Sunnyvale, for fabrication. The new Sun-4 family using the new arrays is expected to relegate the 68020-based Sun-3 line – rated at 4 MIPS – to dhe role of low-end models; its initial incarnation is expected to be as the Sun-4/260, tipped to cost about $50,000 in the monochrome version with 8Mb of memory, $70,000 with colour. Deliveries are expected to begin in late summer, and to be followed by network server and multi-user models later. Sun is also expected to follow the path pioneered by DEC and other major minicomputer manufacturers in the mid-1970s by diversifying into the commercial computing market from a strong base of technical systems. The Sun RISC is believed to implement 93 instructions with an average execution time of 81nS; the company, which declines comment on any forthcoming products or its plans, is thought to want to double the performance of the processor each year by moving to higher levels of integration and winding up the clock. It is also understood to be looking to sell the chip set OEM to other vendors.

White papers from our partners


This article is from the CBROnline archive: some formatting and images may not be present.

CBR Staff Writer

CBR Online legacy content.