STMicroelectronics has adopted the TestKompress automatic test pattern generation, (ATPG) product from Mentor Graphics into its standard 65nm and 45nm design kits.
The new test flow is expected to enable high-quality scan-based production testing for applications such as automotive, cellular infrastructure, and imaging.
According to Mentor Graphics, the high compression capabilities of TestKompress can also be used to implement a low-pin count testing strategy, enabling tests to be applied to a wide variety of components including system in package devices with limited pads for testing. Low-pin count testing can also be used to enable multi-site testing to increase test throughput.
Roberto Mattiuzzo, digital test solutions manager of STMicroelectronics’s technology R&D, central CAD and design solutions, said: With new failure mechanisms at advanced nodes, limitations on IC pins available for testing, and the need to employ better self-test in the field, the range of emerging testing requirements has significantly increased. We are therefore pleased to add Mentor Graphics in the portfolio of electronic data automation solutions supported by STMicroelectronics in the design-for-test area.
Angelo Oldani, design group director in communication infrastructure division of computer and communication infrastructure product group, STMicroelectronics, said: “We have taped out a 65nm design with production testing employing Mentor’s TestKompress product, which enabled us to meet our rigid target in terms of test coverage. Mentor’s strong cooperation and support also helped us to use the LBISTArchitect product to add logic built-in self test (LBIST), allowing device testing in the real application to ensure reliable operation in demanding end-product applications.”
