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December 6, 2010

SMIC adopts Cadence Silicon Realisation products for 65nm SoCss

Integrated end-to-end silicon realisation flow for 65nm system-on-chip designs

By CBR Staff Writer

Cadence Design Systems, a provider of electronic design innovation, said that Semiconductor Manufacturing International (SMIC), the semiconductor foundry in China, had adopted Cadence Silicon Realisation products for the design-for-manufacturing (DFM) and low-power technology at the core of SMIC’s 65-nanometer Reference Flow 4.1.

Using Cadence Encounter Digital Implementation System as the foundation, the companies collaborated to provide an integrated end-to-end silicon realisation flow for 65-nanometre system-on-chip (SoC) designs.

SMIC determined that the tight flow integration across functional, physical, and electrical domains – for estimation, logic design, verification, physical implementation and in-design signoff technologies – provided a boost in both designer productivity and ease of use, and produced results.

Cadence Silicon Realisation technology used in the SMIC flow includes incisive enterprise simulator, encounter RTL compiler, and encounter test, encounter conformal low power.

It also used encounter conformal equivalence checker, encounter digital implementation system, QRC extraction, encounter timing system, encounter power system, litho physical analyser, litho electrical analyser, cadence CMP predictor and sssura physical verification.

Cadence recently announced a new approach to Silicon Realisation that moves chip development patchwork of point tools to a streamlined end-to-end path of integrated technology, tools, and methodology.

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The new approach is focused on offering products and technologies that deliver on the three requirements for a deterministic path to silicon – unified design intent, abstraction, and convergence.

A key element of the Cadence EDA360 strategy, this approach is aimed at boosting productivity, predictability and profitability while reducing risk.

SMIC senior director of design service Min Zhu said their mutual users can benefit from the Cadence contributions to Reference Flow 4.1, which address two important challenges they face at 65nm – design margins and yields.

"Deploying the full end-to-end Cadence Silicon Realisation flow for digital design, verification, and implementation along with our reference flow will enable our users to work more efficiently and productively toward improving silicon quality and shrinking time to market," Zhu said.

Cadence product management group director David Desharnais said working in collaboration with user and design-chain partners like SMIC is key to fulfilling the EDA360 vision and the promise of enhanced productivity, predictability and profitability.

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