Siroyan Technology Ltd has lifted the lid on the Rubicon soft core system-on-a-chip (SoC) architecture which the London, UK company says will deliver true silicon intellectual property (SIP) portability to systems designers (CI No 3718). Siroyan will publish the architecture to prospective silicon founders before the end of this year, with a view to making deliverables, including a compiler and some ASIC libraries, available by the third quarter in 2001.
When prospective partners get their hands on Rubicon, they will see a new approach to SoC design, allowing them to use a single compiler and toolset to develop both general-purpose processor and digital signal processing features on a single device. As well as providing a more elegant solution to modern digital device design, Siroyan’s technology director, Adrian Wise, claims Rubicon will facilitate RISC and DSP performance optimization, reduce development costs, and avoid tying designers into specific toolsets or silicon foundries.
Rubicon is aimed at designers of next generation internet appliances, and as such assumes that general purpose processing and DSP functionality will be a de facto requirement of all its customers. This hybrid architecture will only be available as configurable SoC SIP, and will not be available as a discrete processor. This might impact the performance of Rubicon processors when compared to hard core devices, but its advantage, said Wise, is that it will shorten developers’ lead times and free them from the constraints of proprietary foundry processes.
Also in the interests of shortening development cycles and reducing costs, Siroyan is planning to offer a professional quality tool-chain which can be configured at the same time as the SIP. This should enable developers to test designs against real code during the configuration phase and, critically, Siroyan is planning to make this possible using standard high-level languages. To achieve this Siroyan sees the development of its own compiler as a key strategy. It will be distributed free to interested parties, but its importance lies in the need for a compiler that can optimize code to the very specific architectural features available to designers in the Rubicon architecture.
Although the company has to some extent emphasized the merits of openness and ease of programming over sheer performance, Wise concedes that Rubicon will need to perform to attract adherents. With this is in mind, Siroyan has set itself another daunting challenge, and opted for a clustered very long instruction word (VLIW) approach. To accommodate this, Rubicon makes provision for inter-cluster communication, allowing VLIW to be applied to the problem of realizing instruction level parallelism without swamping the register file with an unmanageable volume of requests for operands from execution units.
Clearly, there are likely to be plenty of hurdles for Siroyan to vault on its journey to delivering Rubicon in a usable form, but Wise is confident that its 18 month time frame is not over ambitious. The company is already, he said, planning what kinds of ASIC library to make available in 2001, but is keeping its plans under wraps until then.
