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Technology / AI and automation


Silicon Graphics Inc’s decision to rewrite its Mips RISC chip roadmap (CI No 3,209), means the first implementation of the company’ next-generation Mips V architecture won’t appear until around the year 2000, instead of 1999. The original Mips V lead, H1, has been scrapped, and all of its engineering resources poured into a re-designed H2 follow-on project. As well as H1 technologies, H2 will include an undisclosed amount of the vector processing requirement used in its Cray Research vector supercomputers, plus other SGI-derived technology including the MDMX Mad Max multimedia extensions. SGI will extend R12000, the next turn of its Mips IV-based R10000 processor, in a line of chips which will start at 300MHz and go up. The advantage of stretching R12000 out puts off further the day when customers will have to recompile to take advantage of a new generation of the instruction set or rebuild systems to accommodate new chip- packaging. New microprocessor designs are usually discussed at industry gatherings such as the Microprocessor Forum which next opens its door in October.

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CBR Staff Writer

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