Shedding more light on SV1, the fourth generation of Cray’s CMOS vector-processing technology, the Silicon Graphics Inc unit says the new architecture includes a new scalar/vector processor which can stream data from main memory through a newly-attached cache and into the vector units. It says this memory system can deliver up to 9.6Gbps bandwidth from the main memory, through cache and into the vector unit, greater than the performance of the existing J90. It enables developers to employ some of the code-blocking techniques long available by their RISC system counterparts. SV1 is the upgrade route for three of Cray’s four vector lines; the J90, and older YMP and C90 generations. As well as scaling to 1,024 CPUs and over 1Tb memory SV1, which runs the Unix-like Unicos, it incorporates a MSP multi-streaming processor comprising four instruction streams delivering the 1GFLOPS processing power promised a few weeks back (CI No 3,422). Application performance improvement is reckoned to be at least 2.5 times after recompilation. SV2, a post-2000 box which replaces SV1’s flat memory with a distributed shared memory system inherited from its SN1 MIPS RISC Origin server cousins at SGI, and will also supersede the high-end T90 vector processor will run a new operating system crafted from SGI’s Irix Unix, Unicos, the Hive Cellular Irix work and more. Over time SGI’s MIPS/Intel-based SN1 architecture will be gradually merged with the SV line.
