Silicon Graphics Inc will hang up its high-end MIPS processor roadmap in 2000 by which time a new, second generation of its MIPS-based Origin ccNUMA Unix servers will be ready for board upgrades to Intel Corp’s IA-64 Merced chip. There won’t be another generation of MIPS chips designed for its servers beyond additional cranks of the R14000 design due in systems early next year. Indeed, SGI expects to offer MIPS, Merced and McKinley servers in parallel for customers which require performance at different price points. It expects commercial users to remain with its MIPS offerings, but given that these customers are few and far between, it expects the majority to move to IA-64. Because there’s no binary compatibility between MIPS and IA-64 (unlike Hewlett-Packard Co’s PA-RISC), switching architectures is going to be more of a wrench for SGI users. SGI says it’s figured out how to support both processors on its ccNUMA ‘Spider’ interconnect but isn’t saying how. Although Merced and McKinley will be offered as module (CPU and memory) upgrades, there will be a separate upgrade required for the I/O subsystems. Emulation simply won’t cut it for its compute-intensive crowd. SGI says the new servers will perform up to 1TFLOP and accommodate up to 1Tb memory. By its reckoning, if Merced does 2GFLOPS, that means the system will accommodate up to 512 CPUs. Clustering takes over thereafter. And clustering using its GSN gigabit system network technologies and other mechanisms will be the subject of a splash SGI is set to make next month for its existing 128-way Origin servers. By 2000 the company’s modular Irix Unix operating system, which is being enhanced with features from the Stanford University Hive project will have been ported to IA-64 implemented in a big-endian byte-ordering format, like Hewlett- Packard Co’s IA-64 systems. SGI says recent analyst observation that Intel’s next-generation 32-bit part, Foster (CI No 3,515), will match Merced’s SPEC performance rating is a misnomer. Merced has far greater floating point functions, more cache, can be used is systems with more than eight CPUs and will meet the requirements of SGI’s technical and scientific customers in a way that Foster or other 32-bit designs will not. Meantime SGI’s MIPS unit is trumpeting shipment of its 100 millionth chip, half of that total in the last three years.
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