Intel prepares to set the RISC world on its ear with N-10 minisupercomputer – on – a – chip While not forgetting that Intel Corp was the onlie begetter of the iAPX-432, which looked like a brilliant chip with all the features needed by fault-tolerant computer manufacturers, PABX builders and embedded systems designers, and yet died a miserable death as a result of a number of factors, most notably lack of software support, the new Intel Corp N-10, described last week at the International Solid State Circuits Conference in New York (CI No 1,118) looks like a runaway winner. Those who nevertheless still feel that there’s many a slip twixt cup and lip will feel vindicated by the fact that the chief designer on the part was also on the team that created the National Semiconductor Corp NS32000, by all accounts a technically splendid microprocessor that nevertheless is a distant number three in the CPU stakes to the Motorola 68000 family and the iAPX-86. Still, give a chip a chance, Intel has learned a bucketful of lessons from the 432 failure, and is today a financially much stronger company with the resources to make sure that there is no skimping on software support. The N-10 is a 1m transistor part in 1 micron CHMOS Intel’s proprietary CMOS process, built around a 64-bit bus and an architecture borrowed from the supercomputer designers. Approximately 330 transistors are devoted to creating the 32-bit integer processor, memory paging unit and bus control unit; an equal amount of real estate accounts for the floating point control unit, adder unit, multiplier unit and three dimensional graphics unit, and the remaining third is devoted mainly to static RAM – the 4Kb instruction cache and the 8Kb data cache, each two-way set associative with 32-bit line size. Since the integer unit, the floating point add and the floating point multiply units can execute in parallel, Intel claims that at peak performance, the thing runs at 150m operations per second when it is clocked at 50MHz – at which speed it dissipates about 3W. Because the caches are on chip, Intel says the thing is able to achieve an aggregate data rate of 1.2Gbytes-per-second. Rated at 105,000 Dhrystones and 21 MFLOPS on the double precision Linpack inner loop benchmark, the part is heavily pipelined, so that as well as concurrent operation of the three separate processing functions, there is a four-stage pipeline in the integer unit to execute integer, control and load/store instructions. By holding load data in the data input latch until the next load, avoiding using a separate port in the register file to store load results, load instructions are executed in one cycle, and because the thing has a 64-bit bus, the 32-bit integer unit can fetch one or two instructions in a single cycle, in the latter case sending one to the integer unit and the other to the floating point unit for parallel execution. There is a five-port floating point register file so that 128-bit floating point load or store instructions can be executed in parallel with floating point instructions, and a pipelined load enables data to be brought from external memory at full bus bandwidth without disturbing the on-board data cache. 21m Gouraud shaded pixels per second The floating point adder can produce a 32-bit or a 64-bit result each cycle, and the floating point multiplier can produce a 32 bit result every cycle and a 64-bit result every two cycles. The three dimensional graphics unit includes Z-buffer and intensity interpolation and can generate up to 21m Gouraud shaded pixels per second with hidden surface elimination. The part measures 10mm by 15mm and comes in a 168-pin package. Intel stresses that the device, work on which started in mid-1986, was conceived from the ground up as a general purpose stand-alone part, and not as a back-end processor for the 80386 and forthcoming 80486. The fact that Intel sees the part as a good emulator for complex mainframe and minicomputer architectures such as the IBM 370 and DEC VAX is intriguing: the company hints that it could perform in the 1990s the resc
ue act that the Advanced Micro Devices Am2901 bit-slice microprocessor performed in the 1970s for smaller companies with proprietary architectures – the Concurrent Computers, Norsk Datas, Prime Computers and Data Generals of the computer world by providing them with a processor that can dramatically reduce the cost of developing powerful new processors on which to run their proprietary software. That is just about all that has been revealed about the N-10 so far, but a formal unveiling to the commercial world is set for Uniforum on February 27.
Seeq describes 1M flash EEPROM Also at the conference, Seeq Technology Inc, San Jose, described what it claims is the world’s first 1M-bit Flash EEPROM, a non volatile part that can be electrically erased and reprogrammed in-circuit very quickly. The 48F010 will come in commercial and military versions, and Seeq also introduced a 1M Flash EPROM, the 27F010, for more cost-sensitive applications. While the premium part can be erased and reprogrammed 1,000 times over the entire operating range, the 27F010 can take only 100 cycles, and at room temperature. The 48F010 is $92 for 100-up, available now; the 27F010 os $78.75 for 100-up. And Texas Instruments Inc said it had developed a static RAM with an 8nS access time.
European Silicon Structures raises $4.5m to get its US2 moving The Dr Robb Wilmot-inspired European Silicon Structures international semiconductor company that likes to be known as ES2 has secured the future of its US arm, now called United Silicon Structures or US2, by reducing its stake in the San Jose, California company to 40%. Three US venture capital firms, Advent International Inc of Boston, Concord Partners of Palo Alto and Mohr Davidow of Menlo Park, have put up a total of $4.5m for a 30% stake, with 30% in the hands of founders and employees. Hitherto little more than an order taking entity for the European company, US2 will use the new cash to establish a US network of distributors, step up marketing, and hire specialists, according to the International Herald Tribune. The new president of US2 is Henry Jarrat, formerly a VLSI Technology Inc vice-president. ES2, which provides software that enables its customers to design their own chips, looks to move into profit in the third quarter of this year, and looks for turnover to double to $28m.