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May 4, 1994


By CBR Staff Writer

As reported briefly, Motorola Inc and IBM Corp took the wraps off their 100MHz PowerPC 604 processor last week. The 32-bit RISC is rated at 160 SPECint92 and 165 Specfp92 – almost double that of the 80MHz 601 – where the Intel Corp Pentium reaches 100 SPECint92 and 80.6 SPECfp92 at 100MHz and won’t hit the latest PowerPC performance marks until the P6 generation. The MPC604 has been optimised for high-end desktops and low-end servers – in symmetric multiprocessing configurations the Somerset team expects it to be used only in systems with up to four or six CPUs; beyond that, the PowerPC 620, due later this year, is expected to take over. Second generation PowerPC Macintoshes and new IBM workstations are seen as initial users of the 604 though 604 systems will likely be expensive to begin with. MPC604 has one floating point unit, but three integer units – two for single clock cycle instructions, the other for integer multiplication and division. Somerset has kept the single-unit floating point performance up with that of three integer units by implementing a new double-precision floating-point algorithm. The part is already sampling in small quantities to highly favoured customers, but general sampling is set to begin in the third quarter with volume production set for the fourth quarter. The unit received first 604 silicon in January.


IBM will fabricate the processor at its Burlington, Vermont facility and Motorola at its MOS-11 factory in Austin, Texas; prices are due in the third quarter. The processor is being fabricated in four-layer, 0.5 micron CMOS, but it is worth noting that the part does not use the new, smaller transistor geometry that made its debut in the 100MHz MPC601. So expect smaller 604s in the future. With 3.6m transistors, the MPC604 takes Somerset’s transistor design count to 8m so far. The 12.4mm by 15.8mm part – at least twice the size of the 603 and a 20% larger than Intel’s P54C Pentium – with two separate 16Kb, four-way set associative instruction and data caches consumes between 8 Watts and 10 Watts in normal use. A ‘nap’ mode takes consumption down to around 400mW. The 604 has an onboard phase-locked loop, which enables the processor to be driven at one, one and a half, two or three times the bus speed. The estimated benchmark was for a 100MHz processor being driven at 1.5 times the 66MHz bus speed, and assumes a compiler optimised for the new chip. The 601 PowerPC, currently at 100MHz will likely get one more revision, possibly to 135MHz, before it is superseded by 604. The 620, Somerset says, will beat out Digital Equipment Corp’s 275MHz Alpha which is due in volume in July. The Somerset team, which is more reticent about its plans than most, promises a PowerPC RoadMap next year, which will show its future plans in more detail. The only guesstimate on what the three-year PowerPC effort has cost so far puts it at $1,000m. The IBM-Motorola Somerset facility has some 250 engineers working on PowerPC design and around 50 other doing the surrounding tool work.

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