When times are good in the memory chip business, manufacturers simply shell out as many standard, undifferentiated parts as they possibly can, and ration them out as fairly as they can among the desperate and insatiable buyers. When times are hard, chipmakers have to batten all the hatches, reduce production activity to the minimum consistent with the health of the plant, and hope to ride out the storm. But the more imaginative will seek to make a little more money by dreaming up enhanced variants of their standard parts that can command a price premium from the relatively small number of users that derive great benefit from more rarefied parts. Synchronous dynamic RAMs that feed out their data in a stream so as to get it where it is wanted faster, started out that way, but they are now commonplace. So now, Samsung Semiconductor Inc, which jealously guards its new-won title as the world’s largest manufacturer of dynamic random access memory chips, has refined the synchronous DRAM by borrowing a technique from microprocessor manufacturers stuck with speed-limited input-output buses. That technique is of course the clock doubler – these days the fastest chips are clock-quintupled – so that all on-chip activity can be conducted at the fastest speed the fabrication technology can handle. And now Samsung os applying clock-doubling to its synchronous memory chips to create what it calls Double-Data Rate SDRAM-II parts. The Double-Data Rate method enables data to be written to or read from the chip at twice the memory bus frequency. Data is sampled on both the rising and falling edges of the clock, effectively doubling the data rate to 133MHz from 66MHz, 200MHz from 100MHz and 300MHz from 150MHz depending on the memory bus frequency. On reads, the chip generates a data strobe or echo clock that is sent with the data to the receiving chip set for synchronisation. Samsung claims that the clock-doubling method can provide up to six times the bandwidth of to- day’s Extended Data Out memory. SDRAM-II is intended to extend synchro- nous technology as the prime main and graphics memory for next year. It is quite happy to have everyone copy it, saying SDRAMII is an open architecture without royalties or fees. Parts will be priced similarly to synchronous memory chips and are expected to go into high-end personal computers and servers, RISC workstations, graphics for personal computers and workstations, and games machines. Initial parts will run at 1.6G-bytes per second with a 100MHz memory bus, and future generations will reach 2.4Gb per second with a 150MHz memory bus. The power drain is 1.6W typical and the first part will be a 64M-bit memory chip. Production starts next year.