Professor David Patterson of the University of California at Berkeley already has two widely-used acronyms – RISC and RAID – attached to his name, but last week the Wall Street Journal attempted to get a third into wider circulation. The Journal ran a long article on the Berkeley Intelligent RAM Project, IRAM, led by Patterson, following a presentation he made at last month’s Hot Chips conference at Stanford. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, enjoy both performance and energy efficiency advantages over conventional systems, say its supporters. IRAM bridges the processor-memory performance, reduces on-chip latency and increases bandwidth. And IRAM architectures permit a much larger amount of memory-on-chip than a traditional SRAM cache design in a logic process. New generation DRAM chips manufactured with technology from the likes of Rambus Inc do little to help, says Patterson, improving bandwidth by 10 times, but at 30% more cost. The bandwidth situation is made worse by higher capacity DRAM chips of 64Mb, 256Mb and beyond. The IRAM concept has been around since the early 1990s, but the project is now attracting funding to the tune of $1m per year from the likes of Intel Corp, Microsoft Corp, Mitsubishi Electric Corp, Micron Technology Inc, Silicon Graphics Inc, Sun Microsystems Inc, IBM Corp and Hitachi Ltd. That doesn’t stop Intel from being skeptical. The Journal quoted Intel spokesman Sunlin Chou as criticizing the technique for requiring a more complicated and more expensive manufacturing process which also requires new machinery. But IRAM also has a rival in the shape of RADram, or reconfigurable architecture DRAM. RADram advocates claim their system has superior yield, higher parallelism, and better integration with commodity microprocessors when compared to IRAM.
