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February 7, 2010

Rambus unveils Mobile XDR memory architecture

Claims to enable future mobile memory platforms that can achieve throughputs of up to 4.3Gbps per pin

By CBR Staff Writer

Rambus has unveiled Mobile XDR memory architecture, which it claims to offer high-bandwidth, low-power memory architecture to enable devices that exceed the power and performance targets for NxG mobile products.

The new memory architecture will enable future mobile memory platforms that can achieve throughputs of up to 4.3Gbps per pin with unequaled power efficiency. The SoC platforms to achieve over 17GB/s of memory bandwidth from a single Mobile XDR DRAM device while extending the battery life of mobile products by more than 30 minutes, the company claims.

The key components of the Mobile XDR memory architecture include Mobile XDR DRAM, Mobile XDR memory controller PHY (MIO) and the Mobile XDR memory controller (MXC), Rambus said.

According to Rambus, its new Mobile XDR memory architecture uses Mobile Memory Initiative innovations including very low-swing differential signaling; FlexClocking Architecture that simplifies the design of the DRAM interface; and advanced power state management that reduces memory system power and provides ultra-fast transition times between various low-power and active operating modes.

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In addition, Rambus’ FlexPhase and Microthreading technologies help enable the power efficiency of the Mobile XDR architecture.

Sharon Holt, senior vice president of licensing and marketing at Rambus, said: “Future mobile applications demand far higher performance and longer battery life than today’s mobile products can achieve. Mobile XDR memory provides the ideal solution for designers to offer leading-edge mobile content in a dramatically lower power and cost-effective manner.

“Uniquely, the Mobile XDR architecture delivers these benefits in SoC and DRAM devices that can be built with current manufacturing infrastructure reducing both risk and time-to-market.”

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