QuickLogic Corp is now shipping QuickTools 5.0, a third party design environment for the pASIC family of field programmable gate arrays. The tool kit comprises its SpDE tool 5.0, design support utilities and third party interface support libraries. It also has an enhanced graphical user interface and additional hypertext-based help files for ease of use. The company claims it can guarantee accurate signal path timing back-annotated to third party simulators in their appropriate design formats. These include EDIF formats from Logic Modeling Corp and Intergraph Corp, Intergraph’s VeriBest and Cadence Design Systems Inc’s Verilog-XL. The new version has optimal buffer insertion, which automatically inserts signal buffers at optimal points in a signal path to improve timing, eliminating the need to tune a device’s performance manually and therefore speeding up and simplyfing the design process. It also has a secondary level of logic optimisation claimed to increase logic density by 12% on average. An 8,000-usable-gate part therefore effectively provides 9,000 usable gates. The version for iAPX-86 operates under both Windows and Windows NT and costs $1,000. Versions for Solaris and HP-UX Unix workstations sell for $2,000. All products are available immediately.
