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April 19, 2004

Power5 OS/400 servers to ship by end of June

Last Thursday, as IBM Corp's CFO, John Joyce, was reviewing sales for the first quarter among the company's various server units, he said that iSeries sales were down 7%, but added that this was due to product transitions. Joyce said further that IBM would be shipping Power5-based iSeries machines by the end of the second quarter.

By CBR Staff Writer

By saying this, Joyce confirmed one set of recent rumors, which said that IBM would ship Power5-based machines in June or July. Another set of rumors said that they would not ship until September or October. IBM’s original Power5 plan was to ship these servers (which were originally code-named Armada, then renamed Squadron) in March or April.

So they are coming out perhaps a bit later than planned. But this is earlier than it could have been, which is good news for iSeries customers, depending on where IBM uses Power5 in the line, when it can actually deliver the servers, and how it prices the boxes.

Analysts suggest that OS/400 V5R3 software for the Squadron machines (and, indeed, all prior S-Star and Power4 AS/400 and iSeries boxes) has been ready for quite some time, and that IBM will announce the software sometime in the next few weeks.

With the OS/400 software ready and everyone waiting for an announcement, IBM can ill afford to wait for the AIX team to catch up and get AIX 5.3 ready. So it looks like OS/400 gets Squadron boxes first. (There was a time when the AS/400 got all the cool new technology first because it was invented in Rochester. It’s good to see this happen again.) IBM can and will slash pSeries prices to keep AIX boxes moving, and it can rely on the high margins in the iSeries line, even with potentially lower prices on Squadron machines, to offset deep discounts on Power4-based pSeries servers until AIX is ready in the fall, if the rumors are right.

If IBM had waited on Power5 with OS/400 to synchronize the OS/400 and AIX announcements on Power5, it would be looking at two more quarters of down sales. I think it is safe to say that loose lips and a lot of pressure from the iSeries team and partner channel got the OS/400-Power5 announcements moved forward to soon rather than later.

Exactly what IBM will announce with the Power5 machines, and what marketing name it will ultimately use to describe them, is unclear. Many think that IBM will have a 4U chassis that delivers from one to four Power5 cores (that’s only two processor cards), as well as an 8U form factor that could scale to either 8 or 16 cores. (It all depends on how many Power5 chips can be crammed into a 4U space without them cooking themselves.)

The architecture of the entry and midrange boxes resembles the approach IBM uses with its Summit family of xSeries Xeon and Itanium servers, where multiple SMP servers are linked to a bigger SMP, via high-speed optical interconnects and NUMA-like SMP clustering. IBM will eventually offer a big Squadron box that scales to 64-way processing (with 128-way virtual processing, thanks to hyper-threading support in the Power5 chip), but that machine may not come out until the fall. If IBM could ship such a big Power5 machine in June, it would not have just launched a 1.9GHz Power4+ processor for the 32-way Regatta-H pSeries machines. This faster 1.9GHz Power4+ chip could, however, finally make its way into the iSeries Model 890 server, which would give IBM’s biggest iSeries customers a little bump in speed for batch processing and some more headroom for online transaction processing.

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Many think it is inevitable that IBM will keep the S-Star processor in the low-end of the current iSeries line, with the Model 800 and Model 810 servers, and play games with the green-screen governors, but there is an outside chance that Power5 will end up in new entry machines, with low prices, no governors, and a tower or rack-mounted packaging option.

In any event, the initial Power5 multichip module packaging, if you trust pictures, shows what looks like four dual-core Power5 processors, each with hyper-threading that makes it look like there are 16 cores on the die, as far as OS/400 and Linux (and eventually AIX) are concerned. That MCM has four 36MB, L3 caches, which is the first time IBM is integrating L3 cache on the chip package.

Each Power5 core has 64KB of L1 cache, and the two cores on a chip share a 1.9MB, L2 cache. The top-end 64-way Squadron box will presumably gang up eight of these Power5 MCMs, which almost certainly will debut at 1.8GHz or higher. Because of the way chips work, IBM has been able to set the clock speed on the MCM versions of its Power chips higher than it can on the entry single-chip versions that appear in low-end and midrange machines.

What IBM will call these Power5-OS/400 boxes officially when they hit the street is the subject of much lip flapping these days. They could be called iSeries–like they are now–or iSeries 500. I’ve heard eServer i5 is being kicked around. I guess we will know when IBM tells us, and even then it is subject to change. Remember, the first generation iSeries machines announced in the summer of 2000 were called AS/400s and then almost immediately rebranded the iSeries 400 in the wake of the big eServer rebranding in October 2000.

This article is based on material originally published by ComputerWire

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