IBM Corp has been quietly sampling a 64-bit PowerPC processor since the spring incorporating more of the compute intensive functions from its high-end Power2 instruction set architecture which has now reached the end of its life. The PowerPC 630 – which IBM is rather confusingly designating Power3, presumably to lend the impression that the Power architecture lives on – will move to Big Blue’s new 0.20 micron copper process later this year, and will show up in new high-end RS/6000 desktops, servers and SP nodes in 1998. IBM says that it never planned to merge the Micro Channel Architecture bus-based, uniprocessor Power instruction architecture with the PCI bus, SMP-enabled PowerPC. Instead it has stripped functionality from Power and incorporated it into PowerPC630/Power3. Power3 accommodates Power2’s superscalar and high-bandwidth design points. Power3 will run both PowerPC and Power2 applications, IBM says. Power3, currently sampling at 200MHz speeds in the 0.25 micron CMOS 6S2 will ramp quickly from 300MHz to 500MHz using the CMOS7S copper process and is expected to deliver 70 SPECfp95 and 30 SPECint95 soon after its first appearance. A design rev to improve the architecture’s associativeness will improve integer performance and make it more attractive for use in systems designed for commercial users, which is currently fulfilled by the 64-bit Apache PowerPC designed by the AS/400 group and used in RS/6000’s Raven SMP servers.
Fastest computer in the world
It’s not clear whether Power3 will be made available to third parties given it’s an IBM architecture and does not emanate from the Somerset PowerPC design shop it shares with Motorola Inc. However given vendors such as Compagne des Machines Bull SA have been dumped on by Somerset’s decision abandon the 64-bit PowerPC 620 chip which Bull had been developing products around, Power3 might yet end up being used in non-IBM devices. The processor core design has two independent, floating-point units, three independent fixed-point units and two load/store units along with aggressive out-of-order and speculative execution and other sophisticated features. It offers a 6.4Gbps connection to L2 cache at 200MHz. It has a 64Kb on-chip data cache and a 32Kb instruction cache. Power3 parts will be used to upgrade the 4,096-processor SP parallel system used by the US Department of Energy at Lawrence Livermore Labs as part of the Accelerated Strategic Computing Initiative (ASCI). IBM claims it’ll deliver 3 TFLOPS making it the fastest computer in the world.
