Sunnyvale, California-based Performance Semiconductor Corp has rushed out another highly integrated version of the MIPS Computer Systems Inc R3000A RISC, the 40MHz PIPER Properly Integrated Performance Easy Rider – whatever that may mean. The PIPER is intended to be used as the CPU in low-end workstations and for embedded control. The part integrates the PR3000A CPU and memory manager, the PR3010A floating point accelerator and a user-programmable cache that can be organised 4Kb for instructions, 4Kb for data or 8Kb instructions and 2Kb data. It operates from a single clock and on chip read-write buffers and bus interface control circuitry eliminates high frequency signals on the external leads. Embedded applications envisaged for the part with cache configures 8Kb-2Kb include graphics control, laser printers, and type setting. When used in the 4Kb-4Kb configuration, it is targeted at low cost desk-top workstations. The part will initially be offered at 35MHz, 40MHz and 45MHz, 40MHz at $143 for 10,000-up for November delivery. It should deliver about 21 MIPS sustained integer performance and 4 MFLOPS double precision Linpack, equivalent to an R3000A, R3010A, 64Kb data and 64Kb instruction cache at 25MHz – at about a third the cost, 10% of the board area. Integrating 1m tran sistors, it will be fabri cated in 0.6 micron CMOS.
