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  1. Technology
February 1, 1989


By CBR Staff Writer

Continuing its determined campaign to take all the pain out of building MS-DOS and OS/2 micros, Chips & Technologies Inc, San Jose, has followed its memory limit buster chip (CI No 1,014) with two cache controllers for 80386-based AT-alikes and PS/Toos. The new 82C307 and 82C327 controllers are designed for use with 20MHz and 25MHz 80386s, and support 16Kb or 32Kb of cache, which should improve performance 25% to 30% – and integrate both cache and main memory control functions on the same chip. The 82C307 is part of the CS8231 Turbo Cache 386/AT set, which provides most of the system logic needed to build 80386 AT-alikes; the 82C327 is a member of the Chip/281 set, with most of the logic for an 80386 PS/Too 70 or 80. The company has also lined up static RAM makers to provide chips optimised for the new sets, and Integrated Device Technology Inc, MOS Electronics Corp and Vitelic Corp have statics ready. Development boards and product design support are available to designers now, and the Chips/281 is sampling now with limited production set for the third quarter. It costs $248.30 for 5,000-up of the 20MHz version, $306.60 for 25MHz. The CS2831 is earlier, with samples now, limited production in March, at $174.80 for 20MHz, $227.20 25MHz, for 5,000-up.

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