A few more details of the ARC core (CI No 3,125) from Argonaut RISC Cores Inc have been dredged up (from a back issue of Electronic Engineering Times, which presumably got them from a spec sheet), and we now know that the 32-bit RISC microprocessor has 32 32-bit general-purpose registers as standard, and supports a 32-bit address space for data and a 24-bit address space for code; it can load and store 32-, 16-or 8-bit data at any 32-bit address. The arithmeticlogic unit uses a four-stage pipeline and supports conditional execution of standard instructions – the base instruction set – with optional flag setting: the base set comprises 15 three-operand instructions and 11 two-operand instructions for basic arithmetic and logic operations, but a host port enables ARC registers to be accessed from another processor for debugging or when an ARC is controlled by a main processor or is part of a multiprocessor architecture. But the key feature is that the architecture provides for up 16 additional three-operand instructions and up to 55 additional two-operand instructions, which any implementor can add to the set – and up to 60 general-purpose 32-bit registers plus additional special-purpose registers are possible, for zero latency access. The part is flexibly extensible and optional modules available include a five-cycle pipelined 32 by 32-bit multiplier, a single-cycle 32-bit barrel-shifter and rotator block and a 16-bit multiplier with optional 36-bit accumulator. A left-shifting 32-bit block is available to find the first significant bit of a word in support of a normal instruction, and a local scratch-pad static RAM supporting a block move to memory.
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