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Technology / AI and automation


National Semiconductor Corp’s NS32000 family of merchant microprocessors may still lag way behind the 68000 and iAPX-86 families in terms of design wins and volume of business, but NatSemi bows to nobody in its dogged determination to make the line a commercial success, nor in the rate at which it upgrades it with higher-performance parts. The 32332 arrived only a year ago, but the company is already set with the NS32532, which integrates the demand-paged virtual memory manager with the CPU, and also adds a 512-byte direct-mapped instruction cache and 1,024-byte two-way set-associative data cache to implement a four-stage pipeline. All of which, claims NatSemi, adds up to about 10 times the performance of the DEC VAX-11/780 and about twice that of the Motorola 68030. The NS32000 has an internal architecture similar to that of the VAX, and is widely regarded by the cognoscenti as a particularly good Unix engine, but still suffers a credibility gap against the Motorola family. Use of on-chip memory management speeds execution by reducing propagation delays, and it can also use half-clock cycles on-chip; virtual-to-physical address translations can also be performed in parallel with other operations such as cache look-ups. The memory manager has an integrated translation lookaside buffer to hold the 64 most recently used virtual addresses and their corresponding physical addresses. The integrated instruction and data caches increase execution speed because external memory does not have to be referenced so often. NatSemi say that it chose a 512 byte instruction cache size because it provided the optimum balance between performance and chip space. The two-way set associative structure of the data cache – for each memory address there are two lines where the address can be placed – means that it performs as though it were a 2Kb direct-mapped cache. The four-stage pipeline comprises a loader, which prefetches instructions and decodes them for the next two steps; an address unit, which calculates effective addresses and prefetches source operands for the following stage; the execution unit, which executes instructions and processes exceptions; and the register file, which holds the program counter and other registers for the address and execution units. The disadvantage of a pipelined machine is that it needs to read ahead to keep the instruction pipeline as full as possible so it tends to prioritise reads over writes, which can lead to a read or write operation to different locations occurring out of execution order – but NatSemi claims that the NS32532 has a special input-output detection mechanism that ensures that read and write operations that are addressed to input-output devices are performed only once and that they are correctly ordered. The 32532 integrates 370,000 transistors in two micron CMOS; NatSemi says it is currently finding fewer than one bug per week and is on target to sample the part in June with volume set for the fourth quarter. It will be $400 to $500 in volume.

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CBR Staff Writer

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